From patchwork Fri Oct 9 15:52:06 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3579 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 6D1E11C2DC1 for ; Fri, 9 Oct 2026 17:56:23 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26568-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26568-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id 53F853AF6A for ; Fri, 9 Oct 2026 15:54:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9E13338E13F; Fri, 9 Oct 2026 15:53:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="JFl/K4Y9" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE82939021A for ; Fri, 9 Oct 2026 15:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.180.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561227; cv=pass; b=kV9hjDbk2dKSUcbHMeS3pJL4wWfMORHYrEyOOYjCJamb1OjurQphhbDiCflRgizyStM91ystDYOpGy5as4LyH6tAeTofiOm6iBngAgZDGeUy0KAnpme5ZHaBJnY4msxBY8LDXH9WLDeXIdKstME+YTvB9kBKYODLQfFGcsqqYrA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561227; c=relaxed/simple; bh=4tu8NvqAIxf9DET9YsURS/31hW2gx+m78Ridy3YKGKk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eeFBNAHTEtEZkidMkOJG7b3EBgQNTpjEcPw6cAFNs5a8ofB1JE0FixoSCJle2cscnt/BRVZqQIGexULj81YCMnDkTwSumYpQk2hJn/FbGAJoErDPPl3XGAF5DYILxc2GPELblz6vkAr/BnkkAiTYCb3HMY99cpqlxeH6sn4uO/w= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=JFl/K4Y9; arc=pass smtp.client-ip=165.173.180.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561194; cv=none; d=zohomail.com; s=zohoarc; b=Ut7gxtmtHWUyVqT2XEXXtWSPb0rp5Mcy7RZLwbX8+UJd1ykj4gOhM+QSm4xoqF+6z/JZODBxX6VDDBUT6itqZWfvfUQgbkWlVncm8rXon3WxpiLxBqtrbpXGiCUDIWm4PKqNNXoYxPplYwWbYfzz0RP3V2ZxmZIsrUVGbFzVXLI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561194; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=kKYL9T0LdCqjHNqPnL4JbPXlqYtxGcuP7NJrPpe/rME=; b=HPCo1KjflXfHvGXp9lF+B9lYvgvCoDS8q4Sz3imUtf03xX3uWWVCm/Am0aKYBKOLdqQxAqsWHVaeuSBpGY2Esc7rBemmbVGQxYJIcyLYUwf+jXOwkFRJPqqDM6JuBAqDgEh7ZylHvC2tEyT6iUOgTGn9ec+XeS3Pr3kgRMD+OAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561194; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=kKYL9T0LdCqjHNqPnL4JbPXlqYtxGcuP7NJrPpe/rME=; b=JFl/K4Y9h6Fj7MgyMfO2EWWSRU6NNb+BWj1Oyc6GOepae0AeDhVHeUQHuOdmbJEw VzybwbFvu8fFLTBcPrCrA1SHRL9DcqhD8MLU29iyOmP3vOoJyNcKa08cmV1rdrJKdez s9Wh10AUNaWnJoPjgKNZ/WnqO8moWGjKFjbfT40c= Received: by smtp.zohomail.com with SMTPS id 1791561192316820.7129077948279; Fri, 9 Oct 2026 08:53:12 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:06 +0800 Subject: [PATCH v6 1/8] dt-bindings: clk: sun60i-a733-ccu: Add Allwinner A733 support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-1-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa , Krzysztof Kozlowski X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=19241; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=4tu8NvqAIxf9DET9YsURS/31hW2gx+m78Ridy3YKGKk=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8m671Hmk1rjOoed2512BjPUME8//OGWkMr+/r+Dun V2yb3g4O0pZGMS4GGTFFFm4/MX/WevwfDsi0HofZg4rE8gQBi5OAZhI0SFGhv/HTdZ7PThc/blA qDPPoFArInqjjk3mEluh9qRbGg9en2T4Zx1beD00vzn/QtENic4DXyVK2oXY+AUK208x8tnqlNv xAQA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [3.34 / 15.00]; RBL_SENDERSCORE(2.00)[172.105.105.114:from]; SUSPICIOUS_RECIPS(1.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; TAGGED_RCPT(0.00)[clk,dt]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=2]; PRECEDENCE_BULK(0.00)[]; DMARC_NA(0.00)[pigmoral.tech]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received]; DBL_BLOCKED_OPENRESOLVER(0.00)[devicetree.org:url,tor.lore.kernel.org:rdns,tor.lore.kernel.org:helo,pigmoral.tech:email,pigmoral.tech:dkim,0.30.140.80:email]; RCPT_COUNT_TWELVE(0.00)[29]; FORGED_SENDER_MAILLIST(0.00)[]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,baylibre.com,gmail.com,arm.com,proton.me,oss.qualcomm.com]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_FIVE(0.00)[5]; FROM_NEQ_ENVFROM(0.00)[junhui.liu@pigmoral.tech,linux-sunxi@lists.linux.dev]; DKIM_TRACE(0.00)[pigmoral.tech:+]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org,pengutronix.de,pigmoral.tech,dabbelt.com,eecs.berkeley.edu,ghiti.fr]; R_SPF_ALLOW(0.00)[+ip4:172.105.105.114:c]; TO_DN_SOME(0.00)[]; R_DKIM_ALLOW(0.00)[pigmoral.tech:s=zmail]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26568-noreply=patchwork.local]; MID_RHS_MATCH_FROM(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: 6D1E11C2DC1 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The CCU and R-CCU (PRCM) modules provide clocks and reset functions for the Allwinner A733 SoC. The clock architecture of the A733 is evolved from the A523, though the root clocking strategy transitions from a static oscillator frequency in the Devicetree to the "hosc" clock, which is determined by choosing from three possible frequencies (19.2MHz, 24MHz, or 26MHz) by the RTC hardware, and finally feeds the CCU and R-CCU. Additionally, the MCU_CCU module found in previous designs is removed from the A733, and the clock tree is expanded with more clock outputs to support new functional modules. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Junhui Liu --- .../bindings/clock/allwinner,sun60i-a733-ccu.yaml | 107 ++++++++ .../dt-bindings/clock/allwinner,sun60i-a733-ccu.h | 291 +++++++++++++++++++++ .../clock/allwinner,sun60i-a733-r-ccu.h | 38 +++ .../dt-bindings/reset/allwinner,sun60i-a733-ccu.h | 129 +++++++++ .../reset/allwinner,sun60i-a733-r-ccu.h | 23 ++ 5 files changed, 588 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file mode 100644 index 000000000000..7c9068d3bbb0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun60i-a733-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A733 Clock Control Unit + +maintainers: + - Junhui Liu + +properties: + compatible: + enum: + - allwinner,sun60i-a733-ccu + - allwinner,sun60i-a733-r-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 7 + + clock-names: + minItems: 4 + maxItems: 7 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: System 24MHz Clock + - description: Peripherals PLL 0 (200 MHz output) + - description: Peripherals PLL 0 (300 MHz output) + - description: Peripherals PLL 1 (300 MHz output) + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: sys-24m + - const: pll-periph0-200m + - const: pll-periph0-300m + - const: pll-periph1-300m + +additionalProperties: false + +examples: + - | + clock-controller@2002000 { + compatible = "allwinner,sun60i-a733-ccu"; + reg = <0x02002000 0x2000>; + clocks = <&osc>, <&rtc 0>, <&rtc 2>, <&rtc 1>; + clock-names = "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h b/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h new file mode 100644 index 000000000000..81924cba58ec --- /dev/null +++ b/include/dt-bindings/clock/allwinner,sun60i-a733-ccu.h @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Junhui Liu + * + * The user manual uses PCLK, HCLK, and MCLK suffixes for some bus clocks. + * These are represented here as APB, AHB, and MBUS prefixes respectively, + * with the bus type moved to the front of the clock name. + */ + +#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_ +#define _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_ + +#define CLK_PLL_REF 0 +#define CLK_SYS_24M 1 +#define CLK_PLL_DDR 2 +#define CLK_PLL_PERIPH0_4X 3 +#define CLK_PLL_PERIPH0_2X 4 +#define CLK_PLL_PERIPH0_800M 5 +#define CLK_PLL_PERIPH0_480M 6 +#define CLK_PLL_PERIPH0_600M 7 +#define CLK_PLL_PERIPH0_400M 8 +#define CLK_PLL_PERIPH0_300M 9 +#define CLK_PLL_PERIPH0_200M 10 +#define CLK_PLL_PERIPH0_160M 11 +#define CLK_PLL_PERIPH0_150M 12 +#define CLK_PLL_PERIPH1_4X 13 +#define CLK_PLL_PERIPH1_2X 14 +#define CLK_PLL_PERIPH1_800M 15 +#define CLK_PLL_PERIPH1_480M 16 +#define CLK_PLL_PERIPH1_600M 17 +#define CLK_PLL_PERIPH1_400M 18 +#define CLK_PLL_PERIPH1_300M 19 +#define CLK_PLL_PERIPH1_200M 20 +#define CLK_PLL_PERIPH1_160M 21 +#define CLK_PLL_PERIPH1_150M 22 +#define CLK_PLL_GPU0 23 +#define CLK_PLL_VIDEO0 24 +#define CLK_PLL_VIDEO0_4X 25 +#define CLK_PLL_VIDEO0_3X 26 +#define CLK_PLL_VIDEO1 27 +#define CLK_PLL_VIDEO1_4X 28 +#define CLK_PLL_VIDEO1_3X 29 +#define CLK_PLL_VIDEO2 30 +#define CLK_PLL_VIDEO2_4X 31 +#define CLK_PLL_VIDEO2_3X 32 +#define CLK_PLL_VE0 33 +#define CLK_PLL_VE1 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO1 36 +#define CLK_PLL_AUDIO1_DIV2 37 +#define CLK_PLL_AUDIO1_DIV5 38 +#define CLK_PLL_NPU 39 +#define CLK_PLL_DE 40 +#define CLK_PLL_DE_4X 41 +#define CLK_PLL_DE_3X 42 +#define CLK_AHB 43 +#define CLK_APB0 44 +#define CLK_APB1 45 +#define CLK_APB_UART 46 +#define CLK_TRACE 47 +#define CLK_GIC 48 +#define CLK_BUS_ITS_PCIE0_ACLK 49 +#define CLK_MBUS 50 +#define CLK_MBUS_IOMMU0_SYS 51 +#define CLK_APB_IOMMU0_SYS 52 +#define CLK_AHB_IOMMU0_SYS 53 +#define CLK_BUS_MSI_LITE0 54 +#define CLK_BUS_MSI_LITE1 55 +#define CLK_BUS_MSI_LITE2 56 +#define CLK_MBUS_IOMMU1_SYS 57 +#define CLK_APB_IOMMU1_SYS 58 +#define CLK_AHB_IOMMU1_SYS 59 +#define CLK_AHB_VE_DEC 60 +#define CLK_AHB_VE_ENC 61 +#define CLK_AHB_VID_IN 62 +#define CLK_AHB_VID_COUT0 63 +#define CLK_AHB_VID_COUT1 64 +#define CLK_AHB_DE 65 +#define CLK_AHB_NPU 66 +#define CLK_AHB_GPU0 67 +#define CLK_AHB_SERDES 68 +#define CLK_AHB_USB_SYS 69 +#define CLK_AHB_MSI_LITE0 70 +#define CLK_AHB_STORE 71 +#define CLK_AHB_CPUS 72 +#define CLK_MBUS_IOMMU0 73 +#define CLK_MBUS_IOMMU1 74 +#define CLK_MBUS_DESYS 75 +#define CLK_MBUS_VE_ENC0_GATE 76 +#define CLK_MBUS_VE_DEC0_GATE 77 +#define CLK_MBUS_GPU0 78 +#define CLK_MBUS_NPU 79 +#define CLK_MBUS_VID_IN 80 +#define CLK_MBUS_SERDES 81 +#define CLK_MBUS_MSI_LITE0 82 +#define CLK_MBUS_STORE 83 +#define CLK_MBUS_MSI_LITE2 84 +#define CLK_MBUS_DMA0 85 +#define CLK_MBUS_VE_ENC0 86 +#define CLK_MBUS_CE 87 +#define CLK_MBUS_DMA1 88 +#define CLK_MBUS_NAND0 89 +#define CLK_MBUS_CSI 90 +#define CLK_MBUS_ISP 91 +#define CLK_MBUS_GMAC0 92 +#define CLK_MBUS_GMAC1 93 +#define CLK_MBUS_VE_DEC0 94 +#define CLK_BUS_DMA0 95 +#define CLK_BUS_DMA1 96 +#define CLK_BUS_SPINLOCK 97 +#define CLK_BUS_MSGBOX0 98 +#define CLK_BUS_PWM0 99 +#define CLK_BUS_PWM1 100 +#define CLK_BUS_DBG 101 +#define CLK_BUS_SYSDAP 102 +#define CLK_TIMER0 103 +#define CLK_TIMER1 104 +#define CLK_TIMER2 105 +#define CLK_TIMER3 106 +#define CLK_TIMER4 107 +#define CLK_TIMER5 108 +#define CLK_TIMER6 109 +#define CLK_TIMER7 110 +#define CLK_TIMER8 111 +#define CLK_TIMER9 112 +#define CLK_BUS_TIMER 113 +#define CLK_AVS 114 +#define CLK_DE0 115 +#define CLK_BUS_DE0 116 +#define CLK_DI 117 +#define CLK_BUS_DI 118 +#define CLK_G2D 119 +#define CLK_BUS_G2D 120 +#define CLK_EINK 121 +#define CLK_EINK_PANEL 122 +#define CLK_BUS_EINK 123 +#define CLK_VE_ENC0 124 +#define CLK_VE_DEC0 125 +#define CLK_BUS_VE_ENC0 126 +#define CLK_BUS_VE_DEC0 127 +#define CLK_CE 128 +#define CLK_BUS_CE 129 +#define CLK_BUS_CE_SYS 130 +#define CLK_NPU 131 +#define CLK_BUS_NPU 132 +#define CLK_GPU0 133 +#define CLK_BUS_GPU0 134 +#define CLK_DRAM0 135 +#define CLK_BUS_DRAM0 136 +#define CLK_NAND0_CLK0 137 +#define CLK_NAND0_CLK1 138 +#define CLK_BUS_NAND0 139 +#define CLK_MMC0 140 +#define CLK_BUS_MMC0 141 +#define CLK_MMC1 142 +#define CLK_BUS_MMC1 143 +#define CLK_MMC2 144 +#define CLK_BUS_MMC2 145 +#define CLK_MMC3 146 +#define CLK_BUS_MMC3 147 +#define CLK_UFS_AXI 148 +#define CLK_UFS_CFG 149 +#define CLK_BUS_UFS 150 +#define CLK_BUS_UART0 151 +#define CLK_BUS_UART1 152 +#define CLK_BUS_UART2 153 +#define CLK_BUS_UART3 154 +#define CLK_BUS_UART4 155 +#define CLK_BUS_UART5 156 +#define CLK_BUS_UART6 157 +#define CLK_BUS_I2C0 158 +#define CLK_BUS_I2C1 159 +#define CLK_BUS_I2C2 160 +#define CLK_BUS_I2C3 161 +#define CLK_BUS_I2C4 162 +#define CLK_BUS_I2C5 163 +#define CLK_BUS_I2C6 164 +#define CLK_BUS_I2C7 165 +#define CLK_BUS_I2C8 166 +#define CLK_BUS_I2C9 167 +#define CLK_BUS_I2C10 168 +#define CLK_BUS_I2C11 169 +#define CLK_BUS_I2C12 170 +#define CLK_SPI0 171 +#define CLK_BUS_SPI0 172 +#define CLK_SPI1 173 +#define CLK_BUS_SPI1 174 +#define CLK_SPI2 175 +#define CLK_BUS_SPI2 176 +#define CLK_SPIF 177 +#define CLK_BUS_SPIF 178 +#define CLK_SPI3 179 +#define CLK_BUS_SPI3 180 +#define CLK_SPI4 181 +#define CLK_BUS_SPI4 182 +#define CLK_GPADC0_24M 183 +#define CLK_BUS_GPADC0 184 +#define CLK_BUS_THS0 185 +#define CLK_IRRX 186 +#define CLK_BUS_IRRX 187 +#define CLK_IRTX 188 +#define CLK_BUS_IRTX 189 +#define CLK_BUS_LRADC 190 +#define CLK_SGPIO 191 +#define CLK_BUS_SGPIO 192 +#define CLK_LPC 193 +#define CLK_BUS_LPC 194 +#define CLK_I2SPCM0 195 +#define CLK_BUS_I2SPCM0 196 +#define CLK_I2SPCM1 197 +#define CLK_BUS_I2SPCM1 198 +#define CLK_I2SPCM2 199 +#define CLK_I2SPCM2_ASRC 200 +#define CLK_BUS_I2SPCM2 201 +#define CLK_I2SPCM3 202 +#define CLK_BUS_I2SPCM3 203 +#define CLK_I2SPCM4 204 +#define CLK_BUS_I2SPCM4 205 +#define CLK_SPDIF_TX 206 +#define CLK_SPDIF_RX 207 +#define CLK_BUS_SPDIF 208 +#define CLK_DMIC 209 +#define CLK_BUS_DMIC 210 +#define CLK_USB_OHCI0 211 +#define CLK_BUS_OHCI0 212 +#define CLK_BUS_EHCI0 213 +#define CLK_BUS_OTG 214 +#define CLK_USB_OHCI1 215 +#define CLK_BUS_OHCI1 216 +#define CLK_BUS_EHCI1 217 +#define CLK_USB01_REF 218 +#define CLK_USB2_U2_REF 219 +#define CLK_USB2_SUSPEND 220 +#define CLK_USB2_MF 221 +#define CLK_USB2_U3_UTMI 222 +#define CLK_USB2_U2_PIPE 223 +#define CLK_PCIE_AUX 224 +#define CLK_PCIE_AXI_SLV 225 +#define CLK_SERDES_PHY 226 +#define CLK_GMAC_PTP 227 +#define CLK_GMAC0_PHY 228 +#define CLK_BUS_GMAC0 229 +#define CLK_GMAC1_PHY 230 +#define CLK_BUS_GMAC1 231 +#define CLK_TCON_LCD0 232 +#define CLK_BUS_TCON_LCD0 233 +#define CLK_TCON_LCD1 234 +#define CLK_BUS_TCON_LCD1 235 +#define CLK_TCON_LCD2 236 +#define CLK_BUS_TCON_LCD2 237 +#define CLK_DSI0 238 +#define CLK_BUS_DSI0 239 +#define CLK_DSI1 240 +#define CLK_BUS_DSI1 241 +#define CLK_COMBPHY0 242 +#define CLK_COMBPHY1 243 +#define CLK_BUS_TCON_TV0 244 +#define CLK_BUS_TCON_TV1 245 +#define CLK_EDP_TV 246 +#define CLK_BUS_EDP_TV 247 +#define CLK_HDMI_CEC_32K 248 +#define CLK_HDMI_CEC 249 +#define CLK_HDMI_TV 250 +#define CLK_BUS_HDMI_TV 251 +#define CLK_HDMI_SFR 252 +#define CLK_HDCP_ESM 253 +#define CLK_BUS_DPSS_TOP0 254 +#define CLK_BUS_DPSS_TOP1 255 +#define CLK_LEDC 256 +#define CLK_BUS_LEDC 257 +#define CLK_BUS_DSC 258 +#define CLK_CSI_MASTER0 259 +#define CLK_CSI_MASTER1 260 +#define CLK_CSI_MASTER2 261 +#define CLK_CSI 262 +#define CLK_BUS_CSI 263 +#define CLK_ISP 264 +#define CLK_RES_DCAP_24M 265 +#define CLK_APB2JTAG 266 +#define CLK_FANOUT_24M 267 +#define CLK_FANOUT_12M 268 +#define CLK_FANOUT_16M 269 +#define CLK_FANOUT_25M 270 +#define CLK_FANOUT_27M 271 +#define CLK_FANOUT_PCLK 272 +#define CLK_FANOUT0 273 +#define CLK_FANOUT1 274 +#define CLK_FANOUT2 275 +#define CLK_FANOUT3 276 + +#endif /* _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_CCU_H_ */ diff --git a/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h b/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h new file mode 100644 index 000000000000..401a1e66e804 --- /dev/null +++ b/include/dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_ +#define _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_R_TIMER3 6 +#define CLK_BUS_R_TIMER 7 +#define CLK_R_PWM 8 +#define CLK_BUS_R_PWM 9 +#define CLK_R_SPI 10 +#define CLK_BUS_R_SPI 11 +#define CLK_BUS_R_MSGBOX 12 +#define CLK_BUS_R_UART0 13 +#define CLK_BUS_R_UART1 14 +#define CLK_BUS_R_I2C0 15 +#define CLK_BUS_R_I2C1 16 +#define CLK_BUS_R_I2C2 17 +#define CLK_BUS_R_PPU 18 +#define CLK_BUS_R_TZMA 19 +#define CLK_BUS_R_CPU_BIST 20 +#define CLK_R_IR_RX 21 +#define CLK_BUS_R_IR_RX 22 +#define CLK_BUS_R_RTC 23 +#define CLK_R_RISCV 24 +#define CLK_BUS_R_RISCV 25 +#define CLK_BUS_R_RISCV_CFG 26 +#define CLK_BUS_R_CPUCFG 27 + +#endif /* _DT_BINDINGS_CLK_ALLWINNER_SUN60I_A733_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h b/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h new file mode 100644 index 000000000000..a4db2f673bd0 --- /dev/null +++ b/include/dt-bindings/reset/allwinner,sun60i-a733-ccu.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_ +#define _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_ + +#define RST_BUS_ITS_PCIE0 0 +#define RST_BUS_IOMMU0_SYS 1 +#define RST_BUS_MSI_LITE0_AHB 2 +#define RST_BUS_MSI_LITE0_MBUS 3 +#define RST_BUS_MSI_LITE1_AHB 4 +#define RST_BUS_MSI_LITE1_MBUS 5 +#define RST_BUS_MSI_LITE2_AHB 6 +#define RST_BUS_MSI_LITE2_MBUS 7 +#define RST_BUS_IOMMU1_SYS 8 +#define RST_BUS_DMA0 9 +#define RST_BUS_DMA1 10 +#define RST_BUS_SPINLOCK 11 +#define RST_BUS_MSGBOX 12 +#define RST_BUS_PWM0 13 +#define RST_BUS_PWM1 14 +#define RST_BUS_DBG 15 +#define RST_BUS_SYSDAP 16 +#define RST_BUS_TIMER0 17 +#define RST_BUS_DE0 18 +#define RST_BUS_DI 19 +#define RST_BUS_G2D 20 +#define RST_BUS_EINK 21 +#define RST_BUS_DE_SYS 22 +#define RST_BUS_VE_ENC0 23 +#define RST_BUS_VE_DEC0 24 +#define RST_BUS_CE 25 +#define RST_BUS_CE_SYS 26 +#define RST_BUS_NPU_CORE 27 +#define RST_BUS_NPU_AXI 28 +#define RST_BUS_NPU_AHB 29 +#define RST_BUS_NPU_SRAM 30 +#define RST_BUS_GPU0 31 +#define RST_BUS_DRAM0 32 +#define RST_BUS_NAND0 33 +#define RST_BUS_MMC0 34 +#define RST_BUS_MMC1 35 +#define RST_BUS_MMC2 36 +#define RST_BUS_MMC3 37 +#define RST_BUS_UFS_AHB 38 +#define RST_BUS_UFS_AXI 39 +#define RST_BUS_UFS_PHY 40 +#define RST_BUS_UFS_CORE 41 +#define RST_BUS_UART0 42 +#define RST_BUS_UART1 43 +#define RST_BUS_UART2 44 +#define RST_BUS_UART3 45 +#define RST_BUS_UART4 46 +#define RST_BUS_UART5 47 +#define RST_BUS_UART6 48 +#define RST_BUS_I2C0 49 +#define RST_BUS_I2C1 50 +#define RST_BUS_I2C2 51 +#define RST_BUS_I2C3 52 +#define RST_BUS_I2C4 53 +#define RST_BUS_I2C5 54 +#define RST_BUS_I2C6 55 +#define RST_BUS_I2C7 56 +#define RST_BUS_I2C8 57 +#define RST_BUS_I2C9 58 +#define RST_BUS_I2C10 59 +#define RST_BUS_I2C11 60 +#define RST_BUS_I2C12 61 +#define RST_BUS_SPI0 62 +#define RST_BUS_SPI1 63 +#define RST_BUS_SPI2 64 +#define RST_BUS_SPIF 65 +#define RST_BUS_SPI3 66 +#define RST_BUS_SPI4 67 +#define RST_BUS_GPADC0 68 +#define RST_BUS_THS0 69 +#define RST_BUS_IRRX 70 +#define RST_BUS_IRTX 71 +#define RST_BUS_LRADC 72 +#define RST_BUS_SGPIO 73 +#define RST_BUS_LPC 74 +#define RST_BUS_I2SPCM0 75 +#define RST_BUS_I2SPCM1 76 +#define RST_BUS_I2SPCM2 77 +#define RST_BUS_I2SPCM3 78 +#define RST_BUS_I2SPCM4 79 +#define RST_BUS_SPDIF 80 +#define RST_BUS_DMIC 81 +#define RST_USB_PHY0 82 +#define RST_BUS_OHCI0 83 +#define RST_BUS_EHCI0 84 +#define RST_BUS_OTG 85 +#define RST_USB_PHY1 86 +#define RST_BUS_OHCI1 87 +#define RST_BUS_EHCI1 88 +#define RST_BUS_USB2 89 +#define RST_BUS_PCIE_PWRUP 90 +#define RST_BUS_PCIE 91 +#define RST_BUS_SERDES 92 +#define RST_BUS_GMAC0 93 +#define RST_BUS_GMAC0_AXI 94 +#define RST_BUS_GMAC1 95 +#define RST_BUS_GMAC1_AXI 96 +#define RST_BUS_TCON_LCD0 97 +#define RST_BUS_TCON_LCD1 98 +#define RST_BUS_TCON_LCD2 99 +#define RST_BUS_LVDS0 100 +#define RST_BUS_LVDS1 101 +#define RST_BUS_DSI0 102 +#define RST_BUS_DSI1 103 +#define RST_BUS_TCON_TV0 104 +#define RST_BUS_TCON_TV1 105 +#define RST_BUS_EDP 106 +#define RST_BUS_HDMI_MAIN 107 +#define RST_BUS_HDMI_SUB 108 +#define RST_BUS_HDMI_HDCP 109 +#define RST_BUS_DPSS_TOP0 110 +#define RST_BUS_DPSS_TOP1 111 +#define RST_BUS_VIDEO_OUT0 112 +#define RST_BUS_VIDEO_OUT1 113 +#define RST_BUS_LEDC 114 +#define RST_BUS_DSC 115 +#define RST_BUS_CSI 116 +#define RST_BUS_VIDEO_IN 117 +#define RST_BUS_APB2JTAG 118 + +#endif /* _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_CCU_H_ */ diff --git a/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h b/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h new file mode 100644 index 000000000000..69fc7d405e1d --- /dev/null +++ b/include/dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_ +#define _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_PWM 1 +#define RST_BUS_R_SPI 2 +#define RST_BUS_R_MSGBOX 3 +#define RST_BUS_R_UART0 4 +#define RST_BUS_R_UART1 5 +#define RST_BUS_R_I2C0 6 +#define RST_BUS_R_I2C1 7 +#define RST_BUS_R_I2C2 8 +#define RST_BUS_R_IR_RX 9 +#define RST_BUS_R_RTC 10 +#define RST_BUS_R_RISCV_CFG 11 +#define RST_BUS_R_CPUCFG 12 + +#endif /* _DT_BINDINGS_RST_ALLWINNER_SUN60I_A733_R_CCU_H_ */ From patchwork Fri Oct 9 15:52:07 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3580 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 581881C2C57 for ; Fri, 9 Oct 2026 17:56:20 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26567-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26567-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id BA2FF3AE48 for ; Fri, 9 Oct 2026 15:54:01 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DA59D38E8C9; Fri, 9 Oct 2026 15:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="JsdTYW2d" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81CA838DC7A for ; Fri, 9 Oct 2026 15:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561226; cv=pass; b=g/UQ1H9PLksxQQ4fAiL2IQvODtMw9WSvYRDM9o6xb3aapuCUMhWDW9iSWa/NXJhB1/sAqaM9knpdvXiEox3xlaHQHs877XvMa4ogbpP9WbPNfTRuBlxvV4lsjpiHlzKemWDUyGOTuD4fTg28J//+iwKmTk/Z0xJJMu0890e4aAg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561226; c=relaxed/simple; bh=8+TlToDAGMcLtBebw/bk3jKYfg+eVBbCP5TQM9k92rA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Twyo3YmKxTQVN6OLzPD+JCkd7E/KkntOnuN3Mmq3ifSJHeBhnWlZ4JcmsMWnCEWRvx9bDrQEbRYTD4cW4VDcv3NvGZ6au4nTY4hIf4Rsg50nVE+T1AORK8Ngbg7NaIDKbfT7Bdc5VEBILuA8NRGYGOT6BCW3CZ3tbGy4t0LAR1o= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=JsdTYW2d; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561204; cv=none; d=zohomail.com; s=zohoarc; b=WogVgt/pwX8Jc3DBK5ZkpHcq7NGOHZMJAkZP4tpKog6qhQqG8gpoUPJ7TMiRquGtvBQ+PRb0qzz1vkupXyQxMOzWeWYPwYrMy5iGQ/yl+FRS/JJPZknEP7O9l1d1slHKVQ/Trw1H45FPHYeH9e201T884iJwKD5AeZ66TtlZ2X8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561204; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=Y9NwEbyVjw2WwQhh/YiuNnChv3bZnD+ix5wp8QNDx/U=; b=FV+eKgvhsmwxW/Eh8F0++XZE+2oBefbj0au5ZBgqb6mm0OZuX1EUJrO+Bwq8WSxEppSb3elbSmQjeeM+L5AFpU6hrftufgjedOXWTpJbsixE7wtSOssUhEe2FhJ46xxkhb4PZx21HHHVfqZqYpXPoA/oeQfTwuxMADUCB0076PA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561204; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Y9NwEbyVjw2WwQhh/YiuNnChv3bZnD+ix5wp8QNDx/U=; b=JsdTYW2dequyeySQjmlil78mdr8ImTeHmCECLcssOVO1owUc0c5Ut4Ytt7QZ0ZUd uYvdpNK13g5PnznUYSbBpyovO6gDegX7OljohROcdVY2TEZdkP4pfctv1hj6vl31gPj iDr9FH6cHxsV/fytfCw8Ars/gGh9tYKJwH/NIBRw= Received: by smtp.zohomail.com with SMTPS id 1791561203109815.1569086105898; Fri, 9 Oct 2026 08:53:23 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:07 +0800 Subject: [PATCH v6 2/8] clk: sunxi-ng: sdm: Add dual patterns support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-2-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5991; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=8+TlToDAGMcLtBebw/bk3jKYfg+eVBbCP5TQM9k92rA=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8u5q47+f/rCpxWde3vrJDC9fFhmqhBgFBqr4iCpkT tQqUC7rKGVhEONikBVTZOHyF/9nrcPz7YhA632YOaxMIEMYuDgFYCJNwowMS8/azez7+OB32lWt i9tTa849fNm06tNGk4qta1wfOB0rcmP4xWQwS6p/5mP3G02O094svhoy/d+W3gABe4P0rJkX+lm WcgMA X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [3.34 / 15.00]; RBL_SENDERSCORE(2.00)[172.105.105.114:from]; SUSPICIOUS_RECIPS(1.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; TAGGED_RCPT(0.00)[clk,dt]; ARC_ALLOW(0.00)[zohomail.com:s=zohoarc:i=2]; PRECEDENCE_BULK(0.00)[]; DMARC_NA(0.00)[pigmoral.tech]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received,165.173.182.15:received]; DBL_BLOCKED_OPENRESOLVER(0.00)[tor.lore.kernel.org:rdns,tor.lore.kernel.org:helo,baylibre.com:email,pigmoral.tech:email,pigmoral.tech:dkim]; RCPT_COUNT_TWELVE(0.00)[28]; FORGED_SENDER_MAILLIST(0.00)[]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,baylibre.com,gmail.com,arm.com,proton.me]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[pigmoral.tech:s=zmail]; FROM_NEQ_ENVFROM(0.00)[junhui.liu@pigmoral.tech,linux-sunxi@lists.linux.dev]; DKIM_TRACE(0.00)[pigmoral.tech:+]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org,pengutronix.de,pigmoral.tech,dabbelt.com,eecs.berkeley.edu,ghiti.fr]; R_SPF_ALLOW(0.00)[+ip4:172.105.105.114]; TO_DN_SOME(0.00)[]; RCVD_COUNT_FIVE(0.00)[5]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26567-noreply=patchwork.local]; MID_RHS_MATCH_FROM(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: 581881C2C57 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= On newer Allwinner platforms like the A733, the Sigma-Delta Modulation (SDM) control logic is more complex. The SDM enable bit, which was previously located in the PLL register, is now moved to a second pattern register (PATTERN1). To support this, rename the existing "tuning" members to "pattern0" to align with the datasheet, and introduce the _SUNXI_CCU_SDM_DUAL_PAT macro to provide pattern1 register support. Related operations are also updated. Tested-by: Jerome Brunet Reviewed-by: Chen-Yu Tsai Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu_sdm.c | 52 ++++++++++++++++++++++++++++++------------ drivers/clk/sunxi-ng/ccu_sdm.h | 29 ++++++++++++++--------- 2 files changed, 55 insertions(+), 26 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c index c564e5f9e610..7e13ffd246d3 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.c +++ b/drivers/clk/sunxi-ng/ccu_sdm.c @@ -18,7 +18,11 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common, if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) return false; - return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable); + if (sdm->pat1_enable && + (readl(common->base + sdm->pat1_reg) & sdm->pat1_enable) != sdm->pat1_enable) + return false; + + return !!(readl(common->base + sdm->pat0_reg) & sdm->pat0_enable); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, "SUNXI_CCU"); @@ -37,18 +41,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common, for (i = 0; i < sdm->table_size; i++) if (sdm->table[i].rate == rate) writel(sdm->table[i].pattern, - common->base + sdm->tuning_reg); + common->base + sdm->pat0_reg); /* Make sure SDM is enabled */ spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + sdm->tuning_reg); - writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); + writel(reg | sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); - spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + common->reg); - writel(reg | sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + common->reg); + writel(reg | sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + sdm->pat1_reg); + writel(reg | sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, "SUNXI_CCU"); @@ -61,14 +74,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common, if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD)) return; - spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + common->reg); - writel(reg & ~sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + common->reg); + writel(reg & ~sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + sdm->pat1_reg); + writel(reg & ~sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + sdm->tuning_reg); - writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); + writel(reg & ~sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, "SUNXI_CCU"); @@ -123,7 +145,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common, pr_debug("%s: clock is sigma-delta modulated\n", clk_hw_get_name(&common->hw)); - reg = readl(common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); pr_debug("%s: pattern reg is 0x%x", clk_hw_get_name(&common->hw), reg); diff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h index c1a7159b89c3..e94cef141c7d 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.h +++ b/drivers/clk/sunxi-ng/ccu_sdm.h @@ -33,21 +33,28 @@ struct ccu_sdm_internal { u32 table_size; /* early SoCs don't have the SDM enable bit in the PLL register */ u32 enable; - /* second enable bit in tuning register */ - u32 tuning_enable; - u16 tuning_reg; + /* second enable bit in pattern0 register */ + u32 pat0_enable; + u16 pat0_reg; + /* on some platforms, the sdm enable bit in pattern1 register */ + u32 pat1_enable; + u16 pat1_reg; }; -#define _SUNXI_CCU_SDM(_table, _enable, \ - _reg, _reg_enable) \ - { \ - .table = _table, \ - .table_size = ARRAY_SIZE(_table), \ - .enable = _enable, \ - .tuning_enable = _reg_enable, \ - .tuning_reg = _reg, \ +#define _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, _pat1, _pat1_enable) \ + { \ + .table = _table, \ + .table_size = ARRAY_SIZE(_table), \ + .enable = _enable, \ + .pat0_enable = _pat0_enable, \ + .pat0_reg = _pat0, \ + .pat1_enable = _pat1_enable, \ + .pat1_reg = _pat1, \ } +#define _SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable) \ + _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, 0, 0) + bool ccu_sdm_helper_is_enabled(struct ccu_common *common, struct ccu_sdm_internal *sdm); void ccu_sdm_helper_enable(struct ccu_common *common, From patchwork Fri Oct 9 15:52:08 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3581 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 75ECB1C2BF5 for ; Fri, 9 Oct 2026 17:58:14 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26569-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26569-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id 4B0F03C978 for ; Fri, 9 Oct 2026 15:54:22 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2408A3793D3; Fri, 9 Oct 2026 15:54:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="ct3uYDng" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60FEF3932D4 for ; Fri, 9 Oct 2026 15:53:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561242; cv=pass; b=ULrQIkwz6rj74zXb8ndgwHsvGLBPgIwUOi/EdTkzV00LocVpzBIuBw7XHKlcI6ATpReAWjqr/edMGk7CVwSnjJBz9kT+kV0PAOzW1br4di7qyrv6k8cnxZWntiHXGv3jaag4TWlkuX4t/0N6qSts0xtuMGmMQW+muhaRw8NaRA4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561242; c=relaxed/simple; bh=AHidVi2xY6vV/upUBfoiEnQg1nkDDrj27MAGYuHxyg0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=smaG86h1FSAymDum5d4v2xoa0uOs+z3+Iz684gX4/CQR3sd9EREyyghEgF8/COCtHjTOpvvdR6MsiVaEVNVdQpRhxlB4CDXpSLdMLhy0CRcNQaksz9eHLJIuZ909q0NcCNFsAGXHmJ7JZLLBG3FNj9NFRolDnBwLZRKtZPHcOBY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=ct3uYDng; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561214; cv=none; d=zohomail.com; s=zohoarc; b=AOTFhAJ+w5zvz1W1/zh/RiarVy3LRWP7gUwGhY9pBnGn2owtch6DFSkvZBdrJdHdzv5uAjrPeIA0S3p2EetIMq4Cro6Mw2f1OsXYshZu4PsR4qWMh/NAA4ZCGOVGM30FGCExnkUOFY6VvQLkcfedOx+u3tpshcatzKlt+DQebls= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561214; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=FKMfoMRxXcyUT/XRcsjJP2U2hfYfBLzVjmtCZOmHZg0=; b=KezygIpXDYwsAjV9NKrahreg49VSEEww2RC3pjgXINq5ZCKPreQe8yLLqoqQ0XQR6xfIFtkDJZgC897SPmdOFutF1mERQ4oOm7ymgQvG8i+B9rD3VxHLHro8Q8GYVmbLg+85GEXhYoqWsE3zbOGNg512pf/p+qQIUm13aiz2ynU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561214; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=FKMfoMRxXcyUT/XRcsjJP2U2hfYfBLzVjmtCZOmHZg0=; b=ct3uYDngO3E8ya0t5VWI/VvNa6MxAG8FuWX16oqy6glXm0zaVK8VQhfbXPGdp863 bM64U0N2zmVkwlQGALp7ScTuQxZoU8eWpm81uSnsvsDX4iL8AscGQmjOZROi4U17+Hd sjWi1dDGzeXFdJy53lGDxjMr0ljuW76nTNbvUXTs= Received: by smtp.zohomail.com with SMTPS id 1791561212401749.6332922678557; Fri, 9 Oct 2026 08:53:32 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:08 +0800 Subject: [PATCH v6 3/8] clk: sunxi-ng: a733: Add PRCM CCU Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-3-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12417; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=AHidVi2xY6vV/upUBfoiEnQg1nkDDrj27MAGYuHxyg0=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8u772BL+nHn3kd7HZaYZK4/b7vgw/YekvJbk4YOT7 mqzfvDq6ShlYRDjYpAVU2Th8hf/Z63D8+2IQOt9mDmsTCBDGLg4BWAik5oZGW78WsYXtZd1WXTU KtF4Nd3uVdEPz7uEzy9P1vzHx+ywsIqR4V6RvMiC4t/bd7PFZM2cz2p7O/JQLd/Tado1zZJnnwm 8ZQMA X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add support for the Power Reset Clock Management (PRCM) module found in the Allwinner A733 SoC. This clock controller manages the clock control and reset functions for device modules within the CPUS domain. The PRCM module includes the management of three primary buses: r-ahb, r-apb0, and r-apb1. It also provides clocking for several key peripherals, such as R-UART, R-I2C, R-SPI, and the R-RISCV subsystem. Additionally, the reset lines for these modules are integrated. Tested-by: Jerome Brunet Reviewed-by: Enzo Adriano Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 277 +++++++++++++++++++++++++++++++ 3 files changed, 284 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6af2d020e03e..202e793dc754 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST +config SUN60I_A733_R_CCU + tristate "Support for the Allwinner A733 PRCM CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a1c4087d7241..d3702bdb7a23 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o @@ -64,6 +65,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun55i-a523-ccu-y += ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o +sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.o sun6i-a31-ccu-y += ccu-sun6i-a31.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file mode 100644 index 000000000000..b8f6e8c6e507 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + * Copyright (C) 2026 Junhui Liu + * Based on the A523 CCU driver: + * Copyright (C) 2024 Arm Ltd. + * + * When secure boot is enabled, firmware must configure PRCM_SEC_SWITCH_REG + * to make the AHBS, APBS0 and APBS1 clock registers accessible to the + * non-secure world. + * + * S_TWD_BGR_REG is fixed to be a secure register regardless of whether + * secure boot is enabled, so it is not described here. + */ + +#include +#include +#include + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" + +static const struct clk_parent_data r_ahb_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .fw_name = "pll-periph0-200m" }, + { .fw_name = "pll-periph0-300m" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb", r_ahb_parents, 0x000, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static const struct clk_parent_data r_apb_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .fw_name = "pll-periph0-200m" }, + { .fw_name = "sys-24m" }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0", r_apb_parents, 0x00c, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1", r_apb_parents, 0x010, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_parents, 0x100, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_parents, 0x104, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", r_apb_parents, 0x108, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_parents, 0x10c, + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); + +static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw, 0x11c, BIT(0), 0); + +static const struct clk_parent_data r_pwm_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .fw_name = "sys-24m" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwm_clk, "r-pwm", r_pwm_parents, 0x130, + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_pwm_clk, "bus-r-pwm", + &r_apb0_clk.common.hw, 0x13c, BIT(0), 0); + +static const struct clk_parent_data r_spi_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "pll-periph0-200m" }, + { .fw_name = "pll-periph0-300m" }, + { .fw_name = "pll-periph1-300m" }, + { .fw_name = "sys-24m" }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi", &r_ahb_clk.common.hw, 0x15c, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.common.hw, 0x17c, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0", &r_apb1_clk.common.hw, 0x18c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1", &r_apb1_clk.common.hw, 0x18c, BIT(1), 0); + +static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, "bus-r-i2c0", &r_apb1_clk.common.hw, 0x19c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, "bus-r-i2c1", &r_apb1_clk.common.hw, 0x19c, BIT(1), 0); +static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, "bus-r-i2c2", &r_apb1_clk.common.hw, 0x19c, BIT(2), 0); + +static SUNXI_CCU_GATE_HW(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_clk.common.hw, 0x1ac, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_tzma_clk, "bus-r-tzma", &r_apb0_clk.common.hw, 0x1b0, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, "bus-r-cpu-bist", &r_apb0_clk.common.hw, + 0x1bc, BIT(0), 0); + +static const struct clk_parent_data r_ir_rx_parents[] = { + { .fw_name = "losc" }, + { .fw_name = "hosc" }, + { .fw_name = "sys-24m" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx", r_ir_rx_parents, 0x1c0, + 0, 5, /* M */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_clk.common.hw, 0x1cc, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_clk.common.hw, 0x20c, BIT(0), 0); + +static const struct clk_parent_data r_riscv_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(r_riscv_clk, "r-riscv", r_riscv_parents, 0x210, + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.common.hw, + 0x21c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_riscv_cfg_clk, "bus-r-riscv-cfg", &r_apb0_clk.common.hw, + 0x21c, BIT(1), 0); + +static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_clk.common.hw, + 0x22c, BIT(0), CLK_IS_CRITICAL); + +static struct ccu_common *sun60i_a733_r_ccu_clks[] = { + &r_ahb_clk.common, + &r_apb0_clk.common, + &r_apb1_clk.common, + &r_cpu_timer0.common, + &r_cpu_timer1.common, + &r_cpu_timer2.common, + &r_cpu_timer3.common, + &bus_r_timer_clk.common, + &r_pwm_clk.common, + &bus_r_pwm_clk.common, + &r_spi_clk.common, + &bus_r_spi_clk.common, + &bus_r_msgbox_clk.common, + &bus_r_uart0_clk.common, + &bus_r_uart1_clk.common, + &bus_r_i2c0_clk.common, + &bus_r_i2c1_clk.common, + &bus_r_i2c2_clk.common, + &bus_r_ppu_clk.common, + &bus_r_tzma_clk.common, + &bus_r_cpu_bist_clk.common, + &r_ir_rx_clk.common, + &bus_r_ir_rx_clk.common, + &bus_r_rtc_clk.common, + &r_riscv_clk.common, + &bus_r_riscv_clk.common, + &bus_r_riscv_cfg_clk.common, + &bus_r_cpucfg_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_a733_r_hw_clks = { + .hws = { + [CLK_R_AHB] = &r_ahb_clk.common.hw, + [CLK_R_APB0] = &r_apb0_clk.common.hw, + [CLK_R_APB1] = &r_apb1_clk.common.hw, + [CLK_R_TIMER0] = &r_cpu_timer0.common.hw, + [CLK_R_TIMER1] = &r_cpu_timer1.common.hw, + [CLK_R_TIMER2] = &r_cpu_timer2.common.hw, + [CLK_R_TIMER3] = &r_cpu_timer3.common.hw, + [CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw, + [CLK_R_PWM] = &r_pwm_clk.common.hw, + [CLK_BUS_R_PWM] = &bus_r_pwm_clk.common.hw, + [CLK_R_SPI] = &r_spi_clk.common.hw, + [CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw, + [CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw, + [CLK_BUS_R_UART0] = &bus_r_uart0_clk.common.hw, + [CLK_BUS_R_UART1] = &bus_r_uart1_clk.common.hw, + [CLK_BUS_R_I2C0] = &bus_r_i2c0_clk.common.hw, + [CLK_BUS_R_I2C1] = &bus_r_i2c1_clk.common.hw, + [CLK_BUS_R_I2C2] = &bus_r_i2c2_clk.common.hw, + [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw, + [CLK_BUS_R_TZMA] = &bus_r_tzma_clk.common.hw, + [CLK_BUS_R_CPU_BIST] = &bus_r_cpu_bist_clk.common.hw, + [CLK_R_IR_RX] = &r_ir_rx_clk.common.hw, + [CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw, + [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw, + [CLK_R_RISCV] = &r_riscv_clk.common.hw, + [CLK_BUS_R_RISCV] = &bus_r_riscv_clk.common.hw, + [CLK_BUS_R_RISCV_CFG] = &bus_r_riscv_cfg_clk.common.hw, + [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw, + }, + .num = CLK_BUS_R_CPUCFG + 1, +}; + +static const struct ccu_reset_map sun60i_a733_r_ccu_resets[] = { + [RST_BUS_R_TIMER] = { 0x11c, BIT(16) }, + [RST_BUS_R_PWM] = { 0x13c, BIT(16) }, + [RST_BUS_R_SPI] = { 0x15c, BIT(16) }, + [RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) }, + [RST_BUS_R_UART0] = { 0x18c, BIT(16) }, + [RST_BUS_R_UART1] = { 0x18c, BIT(17) }, + [RST_BUS_R_I2C0] = { 0x19c, BIT(16) }, + [RST_BUS_R_I2C1] = { 0x19c, BIT(17) }, + [RST_BUS_R_I2C2] = { 0x19c, BIT(18) }, + [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) }, + [RST_BUS_R_RTC] = { 0x20c, BIT(16) }, + [RST_BUS_R_RISCV_CFG] = { 0x21c, BIT(16) }, + [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) }, +}; + +static const struct sunxi_ccu_desc sun60i_a733_r_ccu_desc = { + .ccu_clks = sun60i_a733_r_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun60i_a733_r_ccu_clks), + + .hw_clks = &sun60i_a733_r_hw_clks, + + .resets = sun60i_a733_r_ccu_resets, + .num_resets = ARRAY_SIZE(sun60i_a733_r_ccu_resets), +}; + +static int sun60i_a733_r_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + + reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_r_ccu_desc); +} + +static const struct of_device_id sun60i_a733_r_ccu_ids[] = { + { .compatible = "allwinner,sun60i-a733-r-ccu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sun60i_a733_r_ccu_ids); + +static struct platform_driver sun60i_a733_r_ccu_driver = { + .probe = sun60i_a733_r_ccu_probe, + .driver = { + .name = "sun60i-a733-r-ccu", + .suppress_bind_attrs = true, + .of_match_table = sun60i_a733_r_ccu_ids, + }, +}; +module_platform_driver(sun60i_a733_r_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A733 PRCM CCU"); +MODULE_LICENSE("GPL"); From patchwork Fri Oct 9 15:52:09 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3585 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4]) by mxe881.netcup.net (Postfix) with ESMTPS id DC2591C2BF5 for ; Fri, 9 Oct 2026 18:06:57 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 104.64.211.4) smtp.mailfrom=linux-sunxi+bounces-26570-noreply=patchwork.local@lists.linux.dev smtp.helo=sin.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 104.64.211.4 as permitted sender) client-ip=104.64.211.4; envelope-from=linux-sunxi+bounces-26570-noreply=patchwork.local@lists.linux.dev; helo=sin.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sin.lore.kernel.org (Postfix) with ESMTP id 5F50C2CD54 for ; Fri, 9 Oct 2026 15:54:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 09F76395266; Fri, 9 Oct 2026 15:54:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="hs3oCHGT" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19CBB38E8A2 for ; Fri, 9 Oct 2026 15:54:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561251; cv=pass; b=pCLNpDETFNlRiwArk8PESfROv7LYbsLIGETMfWMtIe5+9n7BSGiJu1ox3pE9EXXXKi8n2KlnlZ28W5E72fbT50XBi5DVQV04Q5UXs281M0z/1s2/GpnwBabvK8SeZ+UY/TxH31oNYaxrTZEw7H4cj+nY862eesURIEbfDEIHLc0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561251; c=relaxed/simple; bh=twUrQ37/M3HTl8xb6jT6r0t7YxQOMK+nWFJ71Ixy0t0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XcGgs9t/XGoqvRpoasS95ysBkeHtkI0PBlqbGBFaffxRgKZpevyweZAnFjkOxzFyuc1tuhfq6BZgGVsLgZ+CC5kzHurLnzXxmsjCFQFNMc4csHKZrgnHr/M1+Q2bUDmu+0u7ufRxlBwyt/Ra1O4QuxCSR37cCEsuscRvjuPOORk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=hs3oCHGT; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561224; cv=none; d=zohomail.com; s=zohoarc; b=cy8v5/Mecp2VKoCrfDzQmCFGWVMXK1ldQ8CyiqF6t6OmrGUZNJgf2WoWHxEC+tSHQhSDTqZqT5aQ0toN5czGK4IXBjZLUuJdbQh0OAZutXF9Mc7xK8G4oWM2mUS+TooM7CyPvz3kuv69HGUKNA/p/r/fCEKgPex3lmLRQTcp6zw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561224; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=+dfh4OfIOXFUS80X4XH5oGBptbxyYny9Oo6n6ZE8I1s=; b=eZjjEMc0074pL+LRS6pLXNELieijp4eH72NktKnSGazlGF+M/Pghwi7aEAaUwh2ZtKFU82plYTQibBDeeTBvqa9TqG+/q1icz986S60Tg6aiB9ZIcrF4FHXxtmS8CzcHlc09pO3nHJgbphzge2isrKUlUUFDShrCm60tFtgY+KA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561224; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=+dfh4OfIOXFUS80X4XH5oGBptbxyYny9Oo6n6ZE8I1s=; b=hs3oCHGTD+Pt1jnZTYWWaJEK+AxmIEdo30/upIDeb5mgoCzcM7ydcvrp711cEkyu 9YfUF3EVdvjYOzZcj965vHmLRKXSJSySoIQG1Er6SlizMEBtUSJ66tslhehD+0OBKqe eKRgLWAbZyamiKPjLZg1X0BRYgVWBs6CvbeOKSPk= Received: by smtp.zohomail.com with SMTPS id 1791561222293146.08575938251943; Fri, 9 Oct 2026 08:53:42 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:09 +0800 Subject: [PATCH v6 4/8] clk: sunxi-ng: a733: Add PLL clocks support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-4-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=23240; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=twUrQ37/M3HTl8xb6jT6r0t7YxQOMK+nWFJ71Ixy0t0=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8h6UVk83OvbDdX2ZbnvT1a0Xcg7Fixw7ILO+6+Hih VvLfQ+4dpSyMIhxMciKKbJw+Yv/s9bh+XZEoPU+zBxWJpAhDFycAjCRiYyMDNeWfDT+wlprEPae pfVzlpLh8fWBSmV9/5SfJPzNsPjvy8zw30XLRXwLa5bXp/s+xR6aQs6R7F2brUN5uvbmLpA7vVq RFwA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs. Model the independently gated outputs of the peripheral, video, and DE PLLs as programmable-divider child clocks, with each output gate modeled separately. Follow the documented hierarchy for the derived peripheral PLL outputs. PLL_AUDIO0 uses SDM parameters from the vendor driver to provide a 22.5792MHz * 4 output. PLL_AUDIO1 provides fixed /2 and /5 outputs and does not expose fractional rates, but its SDM controls are modeled so that stale firmware settings can be disabled when an integer rate is programmed. Tested-by: Jerome Brunet Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 586 +++++++++++++++++++++++++++++++++ 3 files changed, 593 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 202e793dc754..cffa83056934 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST +config SUN60I_A733_CCU + tristate "Support for the Allwinner A733 CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN60I_A733_R_CCU tristate "Support for the Allwinner A733 PRCM CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index d3702bdb7a23..3a39eb9287da 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_CCU) += sun60i-a733-ccu.o obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o @@ -65,6 +66,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun55i-a523-ccu-y += ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o +sun60i-a733-ccu-y += ccu-sun60i-a733.o sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file mode 100644 index 000000000000..3368801053ec --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -0,0 +1,586 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + * Copyright (C) 2026 Junhui Liu + * Based on the A523 CCU driver: + * Copyright (C) 2023-2024 Arm Ltd. + * + * When secure boot is enabled, firmware must configure CCMU_SEC_SWITCH_REG + * to make the PLL, bus and MBUS clock registers accessible to the + * non-secure world. + */ + +#include +#include +#include +#include + +#include +#include + +#include "ccu_common.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mult.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" + +/* + * The DCXO oscillator, the root of most of the clock tree, which may be + * 19.2MHz, 24MHz, or 26MHz. + */ +static const struct clk_parent_data hosc[] = { + { .fw_name = "hosc" } +}; + +/************************************************************************** + * PLLs * + **************************************************************************/ + +/* + * Undocumented, taken from the vendor kernel. + * PLL_REF normalizes the DCXO frequency to a 24MHz reference for downstream + * PLLs. + */ +#define SUN60I_A733_PLL_REF_REG 0x000 +static struct ccu_nkmp pll_ref_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT(8, 8), + .m = _SUNXI_CCU_DIV(16, 7), /* output divider */ + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_REF_REG, + .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ref", hosc, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * Most clock-defining macros expect an *array* of parent clocks, even if + * they do not contain a muxer to select between different parents. + * The macros ending in just _HW take a simple clock pointer, but then create + * a single-entry array out of that. The macros using _HWS take such an + * array (even when it is a single entry one), this avoids having those + * helper arrays created inside *every* clock definition. + * This means for every clock that is referenced more than once it is + * useful to create such a dummy array and use _HWS. + */ +static const struct clk_hw *pll_ref_hws[] = { + &pll_ref_clk.common.hw +}; + +#define SUN60I_A733_PLL_DDR_REG 0x020 +static struct ccu_nkmp pll_ddr_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_DDR_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-ddr", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE | + CLK_IS_CRITICAL), + }, +}; + +/* + * There is no actual clock output with that frequency (2.4 GHz), instead it + * has multiple outputs with adjustable dividers from that base frequency. + * Model them separately as divider clocks based on that parent here. + */ +#define SUN60I_A733_PLL_PERIPH0_REG 0x0a0 +static struct ccu_nm pll_periph0_4x_clk = { + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_PERIPH0_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-periph0-4x", + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph0_4x_hws[] = { + &pll_periph0_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_2x_clk, "pll-periph0-2x", + pll_periph0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, + 20, 3, BIT(27), 0); +static const struct clk_hw *pll_periph0_2x_hws[] = { + &pll_periph0_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_800M_clk, "pll-periph0-800M", + pll_periph0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, + 16, 3, BIT(26), 0); +static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph0_480M_clk, "pll-periph0-480M", + pll_periph0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, + 2, 3, BIT(25), 0); +static const struct clk_hw *pll_periph0_480M_hws[] = { + &pll_periph0_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M", + pll_periph0_2x_hws, 2, 1, 0); +static const struct clk_hw *pll_periph0_600M_hws[] = { + &pll_periph0_600M_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M", + pll_periph0_2x_hws, 3, 1, 0); +static const struct clk_hw *pll_periph0_400M_hws[] = { + &pll_periph0_400M_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", + pll_periph0_600M_hws, 2, 1, 0); +static const struct clk_hw *pll_periph0_300M_hws[] = { + &pll_periph0_300M_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", + pll_periph0_400M_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", + pll_periph0_300M_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", + pll_periph0_480M_hws, 3, 1, 0); + +#define SUN60I_A733_PLL_PERIPH1_REG 0x0c0 +static struct ccu_nm pll_periph1_4x_clk = { + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_PERIPH1_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-periph1-4x", + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph1_4x_hws[] = { + &pll_periph1_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_2x_clk, "pll-periph1-2x", + pll_periph1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, + 20, 3, BIT(27), 0); +static const struct clk_hw *pll_periph1_2x_hws[] = { + &pll_periph1_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_800M_clk, "pll-periph1-800M", + pll_periph1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, + 16, 3, BIT(26), 0); +static SUNXI_CCU_M_HWS_WITH_GATE(pll_periph1_480M_clk, "pll-periph1-480M", + pll_periph1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, + 2, 3, BIT(25), 0); +static const struct clk_hw *pll_periph1_480M_hws[] = { + &pll_periph1_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M", + pll_periph1_2x_hws, 2, 1, 0); +static const struct clk_hw *pll_periph1_600M_hws[] = { + &pll_periph1_600M_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M", + pll_periph1_2x_hws, 3, 1, 0); +static const struct clk_hw *pll_periph1_400M_hws[] = { + &pll_periph1_400M_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M", + pll_periph1_600M_hws, 2, 1, 0); +static const struct clk_hw *pll_periph1_300M_hws[] = { + &pll_periph1_300M_clk.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M", + pll_periph1_400M_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M", + pll_periph1_300M_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M", + pll_periph1_480M_hws, 3, 1, 0); + +#define SUN60I_A733_PLL_GPU_REG 0x0e0 +static struct ccu_nkmp pll_gpu0_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_GPU_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-gpu0", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_VIDEO0_REG 0x120 +static struct ccu_nm pll_video0_clk = { + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_VIDEO0_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-video0", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video0_hws[] = { + &pll_video0_clk.common.hw +}; +static SUNXI_CCU_M_HWS_WITH_GATE(pll_video0_4x_clk, "pll-video0-4x", + pll_video0_hws, SUN60I_A733_PLL_VIDEO0_REG, + 20, 3, BIT(27), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_HWS_WITH_GATE(pll_video0_3x_clk, "pll-video0-3x", + pll_video0_hws, SUN60I_A733_PLL_VIDEO0_REG, + 16, 3, BIT(26), CLK_SET_RATE_PARENT); + +#define SUN60I_A733_PLL_VIDEO1_REG 0x140 +static struct ccu_nm pll_video1_clk = { + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_VIDEO1_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-video1", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video1_hws[] = { + &pll_video1_clk.common.hw +}; +static SUNXI_CCU_M_HWS_WITH_GATE(pll_video1_4x_clk, "pll-video1-4x", + pll_video1_hws, SUN60I_A733_PLL_VIDEO1_REG, + 20, 3, BIT(27), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_HWS_WITH_GATE(pll_video1_3x_clk, "pll-video1-3x", + pll_video1_hws, SUN60I_A733_PLL_VIDEO1_REG, + 16, 3, BIT(26), CLK_SET_RATE_PARENT); + +#define SUN60I_A733_PLL_VIDEO2_REG 0x160 +static struct ccu_nm pll_video2_clk = { + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_VIDEO2_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-video2", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video2_hws[] = { + &pll_video2_clk.common.hw +}; +static SUNXI_CCU_M_HWS_WITH_GATE(pll_video2_4x_clk, "pll-video2-4x", + pll_video2_hws, SUN60I_A733_PLL_VIDEO2_REG, + 20, 3, BIT(27), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_HWS_WITH_GATE(pll_video2_3x_clk, "pll-video2-3x", + pll_video2_hws, SUN60I_A733_PLL_VIDEO2_REG, + 16, 3, BIT(26), CLK_SET_RATE_PARENT); + +#define SUN60I_A733_PLL_VE0_REG 0x220 +static struct ccu_nkmp pll_ve0_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_VE0_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-ve0", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_VE1_REG 0x240 +static struct ccu_nkmp pll_ve1_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_VE1_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-ve1", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * PLL_AUDIO0 has a m1 divider in addition to the usual N, M factors. + * Since we only need some fixed frequency from this PLL (22.5792MHz x 4), + * ignore the divider and force it to 1 (encoded as 0), in the probe function + * below. + * The M factor must be an even number to produce a 50% duty cycle output. + */ +#define SUN60I_A733_PLL_AUDIO0_REG 0x260 +static struct ccu_sdm_setting pll_audio0_sdm_table[] = { + { .rate = 90316800, .pattern = 0xa002872b, .m = 20, .n = 75 }, /* 22.5792 * 4 */ +}; + +static struct ccu_nm pll_audio0_4x_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(16, 7), + .sdm = _SUNXI_CCU_SDM_DUAL_PAT(pll_audio0_sdm_table, 0, + 0x268, BIT(31), + 0x26c, BIT(27) | BIT(31)), + .common = { + .reg = SUN60I_A733_PLL_AUDIO0_REG, + .features = CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-audio0-4x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_AUDIO1_REG 0x280 +static struct ccu_nm pll_audio1_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .sdm = { + /* PLL_AUDIO1 does not use fractional rates. */ + .pat0_enable = BIT(31), + .pat0_reg = 0x288, + .pat1_enable = BIT(27) | BIT(31), + .pat1_reg = 0x28c, + }, + .common = { + .reg = SUN60I_A733_PLL_AUDIO1_REG, + .features = CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-audio1", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_audio1_hws[] = { + &pll_audio1_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, "pll-audio1-div2", + pll_audio1_hws, 2, 1, CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, "pll-audio1-div5", + pll_audio1_hws, 5, 1, CLK_SET_RATE_PARENT); + +#define SUN60I_A733_PLL_NPU_REG 0x2a0 +static struct ccu_nkmp pll_npu_clk = { + .enable = BIT(27), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_NPU_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-npu", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_DE_REG 0x2e0 +static struct ccu_nm pll_de_clk = { + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_DE_REG, + .hw.init = CLK_HW_INIT_PARENTS_HW("pll-de", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_de_hws[] = { + &pll_de_clk.common.hw +}; +static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_4x_clk, "pll-de-4x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, + 20, 3, BIT(27), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_3x_clk, "pll-de-3x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, + 16, 3, BIT(26), CLK_SET_RATE_PARENT); + +/* + * Contains all clocks that are controlled by a hardware register. They + * have a (sunxi) .common member, which needs to be initialised by the common + * sunxi CCU code, to be filled with the MMIO base address and the shared lock. + */ +static struct ccu_common *sun60i_a733_ccu_clks[] = { + &pll_ref_clk.common, + &pll_ddr_clk.common, + &pll_periph0_4x_clk.common, + &pll_periph0_2x_clk.common, + &pll_periph0_800M_clk.common, + &pll_periph0_480M_clk.common, + &pll_periph1_4x_clk.common, + &pll_periph1_2x_clk.common, + &pll_periph1_800M_clk.common, + &pll_periph1_480M_clk.common, + &pll_gpu0_clk.common, + &pll_video0_clk.common, + &pll_video0_4x_clk.common, + &pll_video0_3x_clk.common, + &pll_video1_clk.common, + &pll_video1_4x_clk.common, + &pll_video1_3x_clk.common, + &pll_video2_clk.common, + &pll_video2_4x_clk.common, + &pll_video2_3x_clk.common, + &pll_ve0_clk.common, + &pll_ve1_clk.common, + &pll_audio0_4x_clk.common, + &pll_audio1_clk.common, + &pll_npu_clk.common, + &pll_de_clk.common, + &pll_de_4x_clk.common, + &pll_de_3x_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_a733_hw_clks = { + .hws = { + [CLK_PLL_REF] = &pll_ref_clk.common.hw, + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, + [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw, + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw, + [CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw, + [CLK_PLL_PERIPH0_480M] = &pll_periph0_480M_clk.common.hw, + [CLK_PLL_PERIPH0_600M] = &pll_periph0_600M_clk.hw, + [CLK_PLL_PERIPH0_400M] = &pll_periph0_400M_clk.hw, + [CLK_PLL_PERIPH0_300M] = &pll_periph0_300M_clk.hw, + [CLK_PLL_PERIPH0_200M] = &pll_periph0_200M_clk.hw, + [CLK_PLL_PERIPH0_160M] = &pll_periph0_160M_clk.hw, + [CLK_PLL_PERIPH0_150M] = &pll_periph0_150M_clk.hw, + [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.common.hw, + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.common.hw, + [CLK_PLL_PERIPH1_800M] = &pll_periph1_800M_clk.common.hw, + [CLK_PLL_PERIPH1_480M] = &pll_periph1_480M_clk.common.hw, + [CLK_PLL_PERIPH1_600M] = &pll_periph1_600M_clk.hw, + [CLK_PLL_PERIPH1_400M] = &pll_periph1_400M_clk.hw, + [CLK_PLL_PERIPH1_300M] = &pll_periph1_300M_clk.hw, + [CLK_PLL_PERIPH1_200M] = &pll_periph1_200M_clk.hw, + [CLK_PLL_PERIPH1_160M] = &pll_periph1_160M_clk.hw, + [CLK_PLL_PERIPH1_150M] = &pll_periph1_150M_clk.hw, + [CLK_PLL_GPU0] = &pll_gpu0_clk.common.hw, + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, + [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw, + [CLK_PLL_VIDEO0_3X] = &pll_video0_3x_clk.common.hw, + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, + [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw, + [CLK_PLL_VIDEO1_3X] = &pll_video1_3x_clk.common.hw, + [CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw, + [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.common.hw, + [CLK_PLL_VIDEO2_3X] = &pll_video2_3x_clk.common.hw, + [CLK_PLL_VE0] = &pll_ve0_clk.common.hw, + [CLK_PLL_VE1] = &pll_ve1_clk.common.hw, + [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw, + [CLK_PLL_AUDIO1] = &pll_audio1_clk.common.hw, + [CLK_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.hw, + [CLK_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.hw, + [CLK_PLL_NPU] = &pll_npu_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw, + [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw, + }, + .num = CLK_FANOUT3 + 1, +}; + +static const struct sunxi_ccu_desc sun60i_a733_ccu_desc = { + .ccu_clks = sun60i_a733_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun60i_a733_ccu_clks), + + .hw_clks = &sun60i_a733_hw_clks, +}; + +static const u32 pll_regs[] = { + SUN60I_A733_PLL_REF_REG, + SUN60I_A733_PLL_DDR_REG, + SUN60I_A733_PLL_PERIPH0_REG, + SUN60I_A733_PLL_PERIPH1_REG, + SUN60I_A733_PLL_GPU_REG, + SUN60I_A733_PLL_VIDEO0_REG, + SUN60I_A733_PLL_VIDEO1_REG, + SUN60I_A733_PLL_VIDEO2_REG, + SUN60I_A733_PLL_VE0_REG, + SUN60I_A733_PLL_VE1_REG, + SUN60I_A733_PLL_AUDIO0_REG, + SUN60I_A733_PLL_AUDIO1_REG, + SUN60I_A733_PLL_NPU_REG, + SUN60I_A733_PLL_DE_REG, +}; + +static int sun60i_a733_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + u32 val; + int i, ret; + + reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + /* + * The CCU framework only models one enable bit per PLL, while the + * hardware has separate PLL, LDO, lock, and output gate controls. + * Enable the common PLL, LDO, and lock controls here. + */ + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { + val = readl(reg + pll_regs[i]); + val |= BIT(31) | BIT(30) | BIT(29); + writel(val, reg + pll_regs[i]); + } + + /* Enforce m1 = 0 for PLL_AUDIO0. */ + val = readl(reg + SUN60I_A733_PLL_AUDIO0_REG); + val &= ~BIT(1); + writel(val, reg + SUN60I_A733_PLL_AUDIO0_REG); + + /* Enforce the named /2 and /5 outputs for PLL_AUDIO1. */ + val = readl(reg + SUN60I_A733_PLL_AUDIO1_REG); + val &= ~(GENMASK(22, 20) | GENMASK(18, 16)); + val |= (1 << 20) | (4 << 16); + writel(val, reg + SUN60I_A733_PLL_AUDIO1_REG); + + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_ccu_desc); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id sun60i_a733_ccu_ids[] = { + { .compatible = "allwinner,sun60i-a733-ccu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sun60i_a733_ccu_ids); + +static struct platform_driver sun60i_a733_ccu_driver = { + .probe = sun60i_a733_ccu_probe, + .driver = { + .name = "sun60i-a733-ccu", + .suppress_bind_attrs = true, + .of_match_table = sun60i_a733_ccu_ids, + }, +}; +module_platform_driver(sun60i_a733_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A733 CCU"); +MODULE_LICENSE("GPL"); From patchwork Fri Oct 9 15:52:10 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3582 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 9E07D1C2BF5 for ; Fri, 9 Oct 2026 18:00:41 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26571-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26571-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id E7E7E3E6D2 for ; Fri, 9 Oct 2026 15:54:51 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1931A391E77; Fri, 9 Oct 2026 15:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="U82Fq+Fv" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27A3139CD0B for ; Fri, 9 Oct 2026 15:54:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561255; cv=pass; b=JNDy8KXszQYJ7vK6RALaaAmjc201TtKZ0W6ZVvtF5IIy53MlXSWTd2CsrMAMDpBu5NkfocNoM0EliXM56tTNR6e/8AVIA3jBcq4RNMTZtv9wVzOJcX5jHTyFRTGMe5Ed2VbHKc9AuxkJxQDh1QztPghRDnwx3TFg6Hoh88vt5xY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561255; c=relaxed/simple; bh=Up9pyS/Q2RKqrOglQQX46FNjLPeCngLnf/L5+fqms14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hV0dsTqILOvzUr5jJW543y+VFZA36PX7xi0QPlecOlJpKIA2VUQw/SQ0yfFSQXyFOvBrSMTRy1mug+6aJPsWXcqlyV05wGwDu36Zlj1X5AledYeerMa6qS4/PF5X5/FJnofRusm+YyxcCddaTSg1JTiSId1K4T93uCKX2eAzDzI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=U82Fq+Fv; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561234; cv=none; d=zohomail.com; s=zohoarc; b=gKEvFsWP1jEccmNFzJrpCAutnAb/O4tcl076ghtJqV8CMjuyDPA7a8LT1R8grXgfgws0LisRWdAZYEcPj/hsBpDoZRdPfX7EPr0UwppRDsvwyeXRt/a9feXXvlhHvWaKP978oQWhYzXNnNGN6duU6YqyLm9xDkrMyKuTEuOZopo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561234; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=0rHjHVufduSwcjZK5sRIZ9/auDIPsJFyiZHjGvclrB4=; b=NnzXCEW/fTT/koRhHKhR9lO6zS+awA6XbZdSgmH+1WmfRFOBedqeecFSr9ocRExGvbW4Dz6XNzAqa6D8uyFOQgkeAyfLq7Q7BN81+qDweQsJmu8j1HBWznaxCe0qIV55u4Enb5Imier7oEtI1dPIZujVJtw42ohIb7Bdh+0Xgm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561234; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=0rHjHVufduSwcjZK5sRIZ9/auDIPsJFyiZHjGvclrB4=; b=U82Fq+Fv10ioPI3CBZfF1XrBTzD//2b2SU6ZWiTNGHQ+G0Wl0pct1xKqkRZdR3sS YJIj3wMcZ3ACqDsuYsVkNO2WNX+6mz2Q4W5L42mpb13Fsk3jM7+PDvlohUZQK6cSE8N GkL3QBpczFwzlJS43h/G8wdj4fERBd6QXUeyXzOA= Received: by smtp.zohomail.com with SMTPS id 1791561231859390.2084493010142; Fri, 9 Oct 2026 08:53:51 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:10 +0800 Subject: [PATCH v6 5/8] clk: sunxi-ng: a733: Add bus clocks support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-5-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6643; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=Up9pyS/Q2RKqrOglQQX46FNjLPeCngLnf/L5+fqms14=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8h592pTptSRis9oEqYcTnGTbmFc1Mx7sDVfa4vv4l kJlksv6jlIWBjEuBlkxRRYuf/F/1jo8344ItN6HmcPKBDKEgYtTACayVJmRoT/FeVZfXkb7thNL l+3orMy16Stma/n3ujtVuFzQPiijkJFhy+qucP5DvO0PF8j2rv5+weP5udbpVnfuhbe0PrtnvX8 6LwA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-2.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.105.105.114:from]; SUSPICIOUS_RECIPS(1.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWELVE(0.00)[28]; TAGGED_RCPT(0.00)[clk,dt]; PRECEDENCE_BULK(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; DMARC_NA(0.00)[pigmoral.tech]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,baylibre.com,gmail.com,arm.com,proton.me]; DBL_BLOCKED_OPENRESOLVER(0.00)[pigmoral.tech:email,pigmoral.tech:dkim,tor.lore.kernel.org:rdns,tor.lore.kernel.org:helo,baylibre.com:email]; ARC_ALLOW(0.00)[zohomail.com:s=zohoarc:i=2]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received,165.173.182.15:received]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_FIVE(0.00)[5]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org,pengutronix.de,pigmoral.tech,dabbelt.com,eecs.berkeley.edu,ghiti.fr]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; DKIM_TRACE(0.00)[pigmoral.tech:+]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.105.105.114]; R_DKIM_ALLOW(0.00)[pigmoral.tech:s=zmail]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FROM_NEQ_ENVFROM(0.00)[junhui.liu@pigmoral.tech,linux-sunxi@lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; TAGGED_FROM(0.00)[bounces-26571-noreply=patchwork.local]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: 9E07D1C2BF5 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add the essential bus clocks in the Allwinner A733 CCU, including AHB, APB0, APB1, APB_UART, and MBUS. These buses are necessary for many other functional modules. Additional clocks such as trace and gic are also added as they fall within the register address range of the bus clocks, even though they are not strictly bus clocks. The MBUS clock is marked as critical to ensure the memory bus remains operational at all times. And the hardware requires an update bit (bit 27) to be set so that the configuration takes effect and the updated parameters can be correctly read back for the MBUS clock. The GIC clock is also marked as critical. The bootloader may leave the GIC running on a PLL parent, and disabling that PLL during clk_disable_unused would hang the interrupt controller and the system. Tested-by: Jerome Brunet Reviewed-by: Chen-Yu Tsai Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 108 +++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c index 3368801053ec..371c4297c3ab 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -8,6 +8,9 @@ * When secure boot is enabled, firmware must configure CCMU_SEC_SWITCH_REG * to make the PLL, bus and MBUS clock registers accessible to the * non-secure world. + * + * CPU_PERI_CLK_REG has no documented consumer, while NSI_CLK_REG has no + * known kernel consumer, so they are not modelled here. */ #include @@ -22,6 +25,7 @@ #include "ccu_div.h" #include "ccu_gate.h" +#include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nkmp.h" #include "ccu_nm.h" @@ -72,6 +76,16 @@ static const struct clk_hw *pll_ref_hws[] = { &pll_ref_clk.common.hw }; +/* + * There is a non-software-configurable mux selecting between the DCXO and the + * PLL_REF in hardware, whose output is fed to the sys-24M clock. Although both + * sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor clock to + * provide logical separation: + * - pll-ref is dedicated to feeding other PLLs + * - sys-24M serves as reference clock for downstream functional modules + */ +static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); + #define SUN60I_A733_PLL_DDR_REG 0x020 static struct ccu_nkmp pll_ddr_clk = { .enable = BIT(27), @@ -418,6 +432,85 @@ static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_3x_clk, "pll-de-3x", pll_de_hws, SUN60I_A733_PLL_DE_REG, 16, 3, BIT(26), CLK_SET_RATE_PARENT); +/************************************************************************** + * bus clocks * + **************************************************************************/ + +static const struct clk_parent_data ahb_apb_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static const struct clk_parent_data apb_uart_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x538, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static const struct clk_parent_data trace_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph0_400M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gic_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .hw = &pll_periph0_400M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gic_clk, "gic", gic_parents, 0x560, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL); + +static const struct clk_parent_data mbus_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph1_600M_clk.hw }, + { .hw = &pll_ddr_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .hw = &pll_periph1_400M_clk.hw }, + { .hw = &pll_npu_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the common @@ -452,11 +545,19 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &pll_de_clk.common, &pll_de_4x_clk.common, &pll_de_3x_clk.common, + &ahb_clk.common, + &apb0_clk.common, + &apb1_clk.common, + &apb_uart_clk.common, + &trace_clk.common, + &gic_clk.common, + &mbus_clk.common, }; static struct clk_hw_onecell_data sun60i_a733_hw_clks = { .hws = { [CLK_PLL_REF] = &pll_ref_clk.common.hw, + [CLK_SYS_24M] = &sys_24M_clk.hw, [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw, [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw, @@ -498,6 +599,13 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_PLL_DE] = &pll_de_clk.common.hw, [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw, [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB_UART] = &apb_uart_clk.common.hw, + [CLK_TRACE] = &trace_clk.common.hw, + [CLK_GIC] = &gic_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, }, .num = CLK_FANOUT3 + 1, }; From patchwork Fri Oct 9 15:52:11 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3584 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 1B19A1C3331 for ; Fri, 9 Oct 2026 18:05:56 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26572-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-26572-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 2756085B7A for ; Fri, 9 Oct 2026 15:55:06 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 573793A6F09; Fri, 9 Oct 2026 15:54:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="d+jIsQui" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACF2E3793D3 for ; Fri, 9 Oct 2026 15:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.180.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561266; cv=pass; b=B/r5AhTdqTliuJKu0Dtgoij01K1amGwfcM39lIPxsFcc4xL1+scuAaV2Cs1qLSW1RuuDa/FOe1d8ZLSigEPzweegypdGYArUW84RKQFEfqLfRx8mdqorQVDeNewYNHilU/nigD7UGbBSdk5upP2p7TELgzo0UKyCaDeXaP7MiPE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561266; c=relaxed/simple; bh=qhhHly7kyBaihrDe9n1XloJmdggc9nZsBzW8nno7GZo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a+VQPfzQR/OeVeJMLXzGgFchHPdeayTc/ogiiCKCd+d3IbDuL3V4hDEbRSgv8wZ7yB78VxJqp50gDwirTNIF6thAR8c01yIg+lJKDgSipqtfANvkLYUiZ3xshFS0K4q7a16Iox9HiqGBnlyKN4cYIcfx4etQt6tEkVJGnv5JrSs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=d+jIsQui; arc=pass smtp.client-ip=165.173.180.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561244; cv=none; d=zohomail.com; s=zohoarc; b=c1vDCwxHpBftfUXjUSeXtCgJTHWuT/v6LeHc4fSXbgXmVsG3mTFUeef0lv7d3W7PdGMxGYwL4YldqG6t93o1flDH3aRO0YxFmyNBMkMlqKEmLFkAcr04x71Cb6Uf6H6BNtQgqsO7G+vc3yGU4RO02SCNphOnj7ktzXjMUr9PY2Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561244; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=SpSOJctcGfM5oyvTr+2h0xBtyKSv9XQW0uI3eEg6PLY=; b=Qqz11SsN+JB68tsrp+SBsHFsk4lyj9JZLvUJYVQCw1JmMfolImCVu0cDgL1qCVyc3hyLXWw0h+KMRF2WDxF+ypdpufrhJnnbAN8SW3yZ2LA+bJYj1QIsKGbDMX/8EPwqeutw8aAdcxmf1vCvBIJejdU8aFQ3sBWB+WdH18RJNyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561244; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=SpSOJctcGfM5oyvTr+2h0xBtyKSv9XQW0uI3eEg6PLY=; b=d+jIsQuiiCKCjs9Js2WnIlfzFhWpnDsBMIIfVY9q7dY0ba0EZ94YD/9jrinwSyh0 pa3as32BhSDQDQIYFI98jZzkHgQrPmH1tmD8uUiXzJzU3QpqJ1/aNGbQls+yyFAb8iV aK8kUEKzBCveb1Rbjc+6ywmZECG9i72Chch+6eJ8= Received: by smtp.zohomail.com with SMTPS id 1791561242586441.05849955262875; Fri, 9 Oct 2026 08:54:02 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:11 +0800 Subject: [PATCH v6 6/8] clk: sunxi-ng: a733: Add mod clocks support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-6-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=38814; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=qhhHly7kyBaihrDe9n1XloJmdggc9nZsBzW8nno7GZo=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8p4843Rkxocd7Ww218I4rP3ruFUMxHc//eKRdVWn/ Hjppq4/HaUsDGJcDLJiiixc/uL/rHV4vh0RaL0PM4eVCWQIAxenAExkYTUjw5+Mh52hDDn1rv5c gl4ytmc+GsX/TBAvrly55lbK/TMdWQx/eOfqCvpfTJ3EenE7L+v2j7WFTa8nKd58zZkit976w9Q 8BgA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add the module clocks found in the Allwinner A733 SoC, including video, storage, interfaces and others. While most of these clocks are similar to those in the A523 SoC, this implementation accounts for changes in register offsets and introduces support for new modules. Tested-by: Jerome Brunet Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 1103 ++++++++++++++++++++++++++++++++ 1 file changed, 1103 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c index 371c4297c3ab..7847eec84313 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -27,6 +27,7 @@ #include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" +#include "ccu_mux.h" #include "ccu_nkmp.h" #include "ccu_nm.h" @@ -85,6 +86,9 @@ static const struct clk_hw *pll_ref_hws[] = { * - sys-24M serves as reference clock for downstream functional modules */ static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); +static const struct clk_hw *sys_24M_hws[] = { + &sys_24M_clk.hw +}; #define SUN60I_A733_PLL_DDR_REG 0x020 static struct ccu_nkmp pll_ddr_clk = { @@ -161,6 +165,9 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", pll_periph0_400M_hws, 2, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", pll_periph0_300M_hws, 2, 1, 0); +static const struct clk_hw *pll_periph0_150M_hws[] = { + &pll_periph0_150M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", pll_periph0_480M_hws, 3, 1, 0); @@ -511,6 +518,912 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588 CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); +/************************************************************************** + * mod clocks * + **************************************************************************/ + +static const struct clk_parent_data timer_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "iosc" }, + { .fw_name = "losc" }, + { .hw = &pll_periph0_200M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer0_clk, "timer0", timer_parents, 0x800, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer1_clk, "timer1", timer_parents, 0x804, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer2_clk, "timer2", timer_parents, 0x808, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer3_clk, "timer3", timer_parents, 0x80c, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer4_clk, "timer4", timer_parents, 0x810, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer5_clk, "timer5", timer_parents, 0x814, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer6_clk, "timer6", timer_parents, 0x818, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer7_clk, "timer7", timer_parents, 0x81c, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer8_clk, "timer8", timer_parents, 0x820, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents, 0x824, + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* Undocumented, taken from the vendor kernel. */ +static const struct clk_parent_data avs_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(avs_clk, "avs-clk", avs_parents, 0x880, + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *de_parents[] = { + &pll_de_3x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de0_clk, "de0", de_parents, 0xa00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *di_parents[] = { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *g2d_parents[] = { + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_parents[] = { + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_clk, "eink", eink_parents, 0xa60, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_panel_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video0_3x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_panel_parents, 0xa64, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_enc_parents[] = { + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_enc0_clk, "ve-enc0", ve_enc_parents, 0xa80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_dec_parents[] = { + &pll_ve1_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec0_clk, "ve-dec0", ve_dec_parents, 0xa88, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ce_parents[] = { + &sys_24M_clk.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *npu_parents[] = { + &pll_npu_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_de_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * GPU_CLK = ClockSource * ((16 - M) / 16) + * Here we use a div_table to select M values that result in integer divisors. + */ +static struct clk_div_table gpu_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 8, .div = 2 }, + { .val = 12, .div = 4 }, + { .val = 14, .div = 8 }, + { .val = 15, .div = 16 }, + { /* sentinel */ }, +}; +static const struct clk_parent_data gpu_parents[] = { + { .hw = &pll_gpu0_clk.common.hw, }, + { .hw = &pll_periph0_800M_clk.common.hw, }, + { .hw = &pll_periph0_600M_clk.hw, }, + { .hw = &pll_periph0_400M_clk.hw, }, + { .hw = &pll_periph0_300M_clk.hw, }, + { .hw = &pll_periph0_200M_clk.hw, }, +}; +static struct ccu_div gpu0_clk = { + .enable = BIT(31), + .div = _SUNXI_CCU_DIV_TABLE(0, 4, gpu_div_table), + .mux = _SUNXI_CCU_MUX(24, 3), + .common = { + .reg = 0xb20, + .features = CCU_FEATURE_UPDATE_BIT, + .hw.init = CLK_HW_INIT_PARENTS_DATA("gpu0", gpu_parents, + &ccu_div_ops, 0), + } +}; + +static const struct clk_parent_data dram_parents[] = { + { .hw = &pll_ddr_clk.common.hw, }, + { .hw = &pll_periph0_800M_clk.common.hw, }, + { .hw = &pll_periph0_600M_clk.hw, }, + { .hw = &pll_de_clk.common.hw, }, + { .hw = &pll_npu_clk.common.hw, }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc00, + 0, 4, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); + +static const struct clk_parent_data nand_mmc_parents[] = { + { .hw = &sys_24M_clk.hw, }, + { .hw = &pll_periph0_400M_clk.hw, }, + { .hw = &pll_periph0_300M_clk.hw, }, + { .hw = &pll_periph1_400M_clk.hw, }, + { .hw = &pll_periph1_300M_clk.hw, }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk0_clk, "nand0-clk0", nand_mmc_parents, 0xc80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk1_clk, "nand0-clk1", nand_mmc_parents, 0xc84, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, 0xd00, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, 0xd10, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); + +static const struct clk_parent_data mmc2_mmc3_parents[] = { + { .hw = &sys_24M_clk.hw, }, + { .hw = &pll_periph0_800M_clk.common.hw }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph1_800M_clk.common.hw }, + { .hw = &pll_periph1_600M_clk.hw }, +}; +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_parents, 0xd20, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parents, 0xd30, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); + +static const struct clk_hw *ufs_axi_parents[] = { + &pll_periph0_300M_clk.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ufs_axi_clk, "ufs-axi", ufs_axi_parents, 0xd80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data ufs_cfg_parents[] = { + { .hw = &pll_periph0_480M_clk.common.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_parents, 0xd84, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data spi_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph0_200M_clk.hw }, + { .hw = &pll_periph1_300M_clk.hw }, + { .hw = &pll_periph1_200M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .fw_name = "hosc"}, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0xf08, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0xf10, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data spif_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_400M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph1_400M_clk.hw }, + { .hw = &pll_periph1_300M_clk.hw }, + { .hw = &pll_periph0_160M_clk.hw }, + { .hw = &pll_periph1_160M_clk.hw }, + { .fw_name = "hosc"}, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, "spi3", spi_parents, 0xf20, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gpadc0_24m_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc0_24m_clk, "gpadc0-24m", gpadc0_24m_parents, 0xfc0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data irrx_parents[] = { + { .fw_name = "losc"}, + { .hw = &sys_24M_clk.hw }, + { .fw_name = "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x1000, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data irtx_parents[] = { + { .fw_name = "losc"}, + { .hw = &pll_periph1_600M_clk.hw }, + { .fw_name = "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x1008, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* Undocumented, taken from the vendor kernel. */ +static const struct clk_parent_data sgpio_parents[] = { + { .fw_name = "losc"}, + { .hw = &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0x1060, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* Undocumented, taken from the vendor kernel. */ +static const struct clk_hw *lpc_parents[] = { + &pll_video0_3x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_video2_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *i2spcm_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.hw, + &pll_audio1_div5_clk.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents, 0x1200, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, "i2spcm1", i2spcm_parents, 0x1210, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents, 0x1220, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *i2spcm2_asrc_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.hw, + &pll_audio1_div5_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_periph1_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2spcm2_asrc_parents, 0x1224, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents, 0x1230, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents, 0x1240, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *spdif_tx_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.hw, + &pll_audio1_div5_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", spdif_tx_parents, 0x1280, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *spdif_rx_parents[] = { + &pll_periph0_200M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0x1284, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *dmic_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.hw, + &pll_audio1_div5_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is + * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also used by + * the OHCI module. + */ +static const struct clk_parent_data usb_ohci_parents[] = { + { .hw = &pll_periph0_4x_clk.common.hw }, + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, +}; +static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = { + { .index = 0, .div = 200 }, + { .index = 1, .div = 2 }, +}; + +static struct ccu_mux usb_ohci0_clk = { + .enable = BIT(31), + .mux = { + .shift = 24, + .width = 2, + .fixed_predivs = usb_ohci_predivs, + .n_predivs = ARRAY_SIZE(usb_ohci_predivs), + }, + .common = { + .reg = 0x1300, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0", usb_ohci_parents, + &ccu_mux_ops, 0), + }, +}; + +static struct ccu_mux usb_ohci1_clk = { + .enable = BIT(31), + .mux = { + .shift = 24, + .width = 2, + .fixed_predivs = usb_ohci_predivs, + .n_predivs = ARRAY_SIZE(usb_ohci_predivs), + }, + .common = { + .reg = 0x1308, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1", usb_ohci_parents, + &ccu_mux_ops, 0), + }, +}; + +static const struct clk_parent_data usb01_ref_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_MUX_DATA(usb01_ref_clk, "usb01-ref", usb01_ref_parents, 0x1340, 24, 3, 0); + +static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb01_ref_parents, 0x1348, 24, 3, 0); + +static const struct clk_parent_data usb2_suspend_parents[] = { + { .fw_name = "losc" }, + { .hw = &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_suspend_clk, "usb2-suspend", usb2_suspend_parents, + 0x1350, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_mf_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_mf_clk, "usb2-mf", usb2_mf_parents, + 0x1354, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_u3_utmi_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u3_utmi_clk, "usb2-u3-utmi", usb2_u3_utmi_parents, + 0x1360, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_u2_pipe_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u2_pipe_clk, "usb2-u2-pipe", usb2_u2_pipe_parents, + 0x1364, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data pcie_aux_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", pcie_aux_parents, 0x1380, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *pcie_axi_slv_parents[] = { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(pcie_axi_slv_clk, "pcie-axi-slv", pcie_axi_slv_parents, 0x1384, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *serdes_phy_parents[] = { + &sys_24M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(serdes_phy_clk, "serdes-phy", serdes_phy_parents, 0x13c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gmac_ptp_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_200M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gmac_ptp_clk, "gmac-ptp", gmac_ptp_parents, 0x1400, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_150M_hws, 0x1410, + 0, 5, /* M */ + BIT(31), /* gate */ + 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac1-phy", pll_periph0_150M_hws, 0x1420, + 0, 5, /* M */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *tcon_lcd_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_parents, 0x1500, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_parents, 0x1508, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", tcon_lcd_parents, 0x1510, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *dsi_parents[] = { + &sys_24M_clk.hw, + &pll_periph0_200M_clk.hw, + &pll_periph0_150M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *combphy_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, + &pll_video0_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy0_clk, "combphy0", combphy_parents, 0x15c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_parents, 0x15c4, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *edp_tv_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, 0x1640, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pll_periph0_2x_hws, 0x1680, + BIT(30), /* gate */ + 36621, /* pre div */ + 0); + +static const struct clk_parent_data hdmi_cec_parents[] = { + { .fw_name = "losc" }, + { .hw = &hdmi_cec_32k_clk.common.hw }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0x1680, + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data hdmi_tv_parents[] = { + { .hw = &pll_video0_4x_clk.common.hw }, + { .hw = &pll_video1_4x_clk.common.hw }, + { .hw = &pll_video2_4x_clk.common.hw }, + { .hw = &pll_periph0_2x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents, 0x1684, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data hdmi_sfr_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_parents, 0x1690, + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(hdcp_esm_clk, "hdcp-esm", pll_periph0_300M_hws, 0x1694, BIT(31), 0); + +static const struct clk_parent_data ledc_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_600M_clk.hw }, + { .fw_name = "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x1700, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data csi_master_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_video0_4x_clk.common.hw }, + { .hw = &pll_video0_3x_clk.common.hw }, + { .hw = &pll_video1_4x_clk.common.hw }, + { .hw = &pll_video1_3x_clk.common.hw }, + { .hw = &pll_video2_4x_clk.common.hw }, + { .hw = &pll_video2_3x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master0_clk, "csi_master0", csi_master_parents, 0x1800, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master1_clk, "csi_master1", csi_master_parents, 0x1804, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master2_clk, "csi_master2", csi_master_parents, 0x1808, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *csi_parents[] = { + &pll_video2_4x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *isp_parents[] = { + &pll_video2_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0x1860, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_DATA(res_dcap_24m_clk, "res-dcap-24m", hosc, 0x1a00, BIT(3), 0); + +static const struct clk_parent_data apb2jtag_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .hw = &pll_periph0_200M_clk.hw }, + { .hw = &pll_periph1_200M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(apb2jtag_clk, "apb2jtag", apb2jtag_parents, 0x1c00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(fanout_24M_clk, "fanout-24M", sys_24M_hws, 0x1f30, BIT(0), 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_12M_clk, "fanout-12M", sys_24M_hws, 0x1f30, + BIT(1), 2, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_480M_hws, 0x1f30, + BIT(2), 30, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_2x_hws, 0x1f30, + BIT(3), 48, 0); + +static const struct clk_parent_data fanout_27M_parents[] = { + { .hw = &pll_video0_4x_clk.common.hw }, + { .hw = &pll_video1_4x_clk.common.hw }, + { .hw = &pll_video2_4x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0x1f34, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data fanout_pclk_parents[] = { + { .hw = &apb0_clk.common.hw } +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk", fanout_pclk_parents, 0x1f38, + 0, 5, /* M */ + 5, 5, /* N */ + 0, 0, /* no mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data fanout_parents[] = { + { .fw_name = "losc-fanout" }, + { .hw = &fanout_12M_clk.common.hw, }, + { .hw = &fanout_16M_clk.common.hw, }, + { .hw = &fanout_24M_clk.common.hw, }, + { .hw = &fanout_25M_clk.common.hw, }, + { .hw = &fanout_27M_clk.common.hw, }, + { .hw = &fanout_pclk_clk.common.hw, }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0x1f3c, + 0, 3, /* mux */ + BIT(21), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0x1f3c, + 3, 3, /* mux */ + BIT(22), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0x1f3c, + 6, 3, /* mux */ + BIT(23), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout3_clk, "fanout3", fanout_parents, 0x1f3c, + 9, 3, /* mux */ + BIT(24), /* gate */ + 0); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the common @@ -552,6 +1465,101 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &trace_clk.common, &gic_clk.common, &mbus_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &timer2_clk.common, + &timer3_clk.common, + &timer4_clk.common, + &timer5_clk.common, + &timer6_clk.common, + &timer7_clk.common, + &timer8_clk.common, + &timer9_clk.common, + &avs_clk.common, + &de0_clk.common, + &di_clk.common, + &g2d_clk.common, + &eink_clk.common, + &eink_panel_clk.common, + &ve_enc0_clk.common, + &ve_dec0_clk.common, + &ce_clk.common, + &npu_clk.common, + &gpu0_clk.common, + &dram0_clk.common, + &nand0_clk0_clk.common, + &nand0_clk1_clk.common, + &mmc0_clk.common, + &mmc1_clk.common, + &mmc2_clk.common, + &mmc3_clk.common, + &ufs_axi_clk.common, + &ufs_cfg_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spif_clk.common, + &spi3_clk.common, + &spi4_clk.common, + &gpadc0_24m_clk.common, + &irrx_clk.common, + &irtx_clk.common, + &sgpio_clk.common, + &lpc_clk.common, + &i2spcm0_clk.common, + &i2spcm1_clk.common, + &i2spcm2_clk.common, + &i2spcm2_asrc_clk.common, + &i2spcm3_clk.common, + &i2spcm4_clk.common, + &spdif_tx_clk.common, + &spdif_rx_clk.common, + &dmic_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &usb01_ref_clk.common, + &usb2_u2_ref_clk.common, + &usb2_suspend_clk.common, + &usb2_mf_clk.common, + &usb2_u3_utmi_clk.common, + &usb2_u2_pipe_clk.common, + &pcie_aux_clk.common, + &pcie_axi_slv_clk.common, + &serdes_phy_clk.common, + &gmac_ptp_clk.common, + &gmac0_phy_clk.common, + &gmac1_phy_clk.common, + &tcon_lcd0_clk.common, + &tcon_lcd1_clk.common, + &tcon_lcd2_clk.common, + &dsi0_clk.common, + &dsi1_clk.common, + &combphy0_clk.common, + &combphy1_clk.common, + &edp_tv_clk.common, + &hdmi_cec_32k_clk.common, + &hdmi_cec_clk.common, + &hdmi_tv_clk.common, + &hdmi_sfr_clk.common, + &hdcp_esm_clk.common, + &ledc_clk.common, + &csi_master0_clk.common, + &csi_master1_clk.common, + &csi_master2_clk.common, + &csi_clk.common, + &isp_clk.common, + &res_dcap_24m_clk.common, + &apb2jtag_clk.common, + &fanout_24M_clk.common, + &fanout_12M_clk.common, + &fanout_16M_clk.common, + &fanout_25M_clk.common, + &fanout_27M_clk.common, + &fanout_pclk_clk.common, + &fanout0_clk.common, + &fanout1_clk.common, + &fanout2_clk.common, + &fanout3_clk.common, }; static struct clk_hw_onecell_data sun60i_a733_hw_clks = { @@ -606,6 +1614,101 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_TRACE] = &trace_clk.common.hw, [CLK_GIC] = &gic_clk.common.hw, [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_TIMER0] = &timer0_clk.common.hw, + [CLK_TIMER1] = &timer1_clk.common.hw, + [CLK_TIMER2] = &timer2_clk.common.hw, + [CLK_TIMER3] = &timer3_clk.common.hw, + [CLK_TIMER4] = &timer4_clk.common.hw, + [CLK_TIMER5] = &timer5_clk.common.hw, + [CLK_TIMER6] = &timer6_clk.common.hw, + [CLK_TIMER7] = &timer7_clk.common.hw, + [CLK_TIMER8] = &timer8_clk.common.hw, + [CLK_TIMER9] = &timer9_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_DE0] = &de0_clk.common.hw, + [CLK_DI] = &di_clk.common.hw, + [CLK_G2D] = &g2d_clk.common.hw, + [CLK_EINK] = &eink_clk.common.hw, + [CLK_EINK_PANEL] = &eink_panel_clk.common.hw, + [CLK_VE_ENC0] = &ve_enc0_clk.common.hw, + [CLK_VE_DEC0] = &ve_dec0_clk.common.hw, + [CLK_CE] = &ce_clk.common.hw, + [CLK_NPU] = &npu_clk.common.hw, + [CLK_GPU0] = &gpu0_clk.common.hw, + [CLK_DRAM0] = &dram0_clk.common.hw, + [CLK_NAND0_CLK0] = &nand0_clk0_clk.common.hw, + [CLK_NAND0_CLK1] = &nand0_clk1_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_UFS_AXI] = &ufs_axi_clk.common.hw, + [CLK_UFS_CFG] = &ufs_cfg_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_SPIF] = &spif_clk.common.hw, + [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_SPI4] = &spi4_clk.common.hw, + [CLK_GPADC0_24M] = &gpadc0_24m_clk.common.hw, + [CLK_IRRX] = &irrx_clk.common.hw, + [CLK_IRTX] = &irtx_clk.common.hw, + [CLK_SGPIO] = &sgpio_clk.common.hw, + [CLK_LPC] = &lpc_clk.common.hw, + [CLK_I2SPCM0] = &i2spcm0_clk.common.hw, + [CLK_I2SPCM1] = &i2spcm1_clk.common.hw, + [CLK_I2SPCM2] = &i2spcm2_clk.common.hw, + [CLK_I2SPCM2_ASRC] = &i2spcm2_asrc_clk.common.hw, + [CLK_I2SPCM3] = &i2spcm3_clk.common.hw, + [CLK_I2SPCM4] = &i2spcm4_clk.common.hw, + [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw, + [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw, + [CLK_DMIC] = &dmic_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_USB01_REF] = &usb01_ref_clk.common.hw, + [CLK_USB2_U2_REF] = &usb2_u2_ref_clk.common.hw, + [CLK_USB2_SUSPEND] = &usb2_suspend_clk.common.hw, + [CLK_USB2_MF] = &usb2_mf_clk.common.hw, + [CLK_USB2_U3_UTMI] = &usb2_u3_utmi_clk.common.hw, + [CLK_USB2_U2_PIPE] = &usb2_u2_pipe_clk.common.hw, + [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw, + [CLK_PCIE_AXI_SLV] = &pcie_axi_slv_clk.common.hw, + [CLK_SERDES_PHY] = &serdes_phy_clk.common.hw, + [CLK_GMAC_PTP] = &gmac_ptp_clk.common.hw, + [CLK_GMAC0_PHY] = &gmac0_phy_clk.common.hw, + [CLK_GMAC1_PHY] = &gmac1_phy_clk.common.hw, + [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, + [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, + [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw, + [CLK_DSI0] = &dsi0_clk.common.hw, + [CLK_DSI1] = &dsi1_clk.common.hw, + [CLK_COMBPHY0] = &combphy0_clk.common.hw, + [CLK_COMBPHY1] = &combphy1_clk.common.hw, + [CLK_EDP_TV] = &edp_tv_clk.common.hw, + [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw, + [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, + [CLK_HDMI_TV] = &hdmi_tv_clk.common.hw, + [CLK_HDMI_SFR] = &hdmi_sfr_clk.common.hw, + [CLK_HDCP_ESM] = &hdcp_esm_clk.common.hw, + [CLK_LEDC] = &ledc_clk.common.hw, + [CLK_CSI_MASTER0] = &csi_master0_clk.common.hw, + [CLK_CSI_MASTER1] = &csi_master1_clk.common.hw, + [CLK_CSI_MASTER2] = &csi_master2_clk.common.hw, + [CLK_CSI] = &csi_clk.common.hw, + [CLK_ISP] = &isp_clk.common.hw, + [CLK_RES_DCAP_24M] = &res_dcap_24m_clk.common.hw, + [CLK_APB2JTAG] = &apb2jtag_clk.common.hw, + [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw, + [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw, + [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw, + [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw, + [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw, + [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw, + [CLK_FANOUT0] = &fanout0_clk.common.hw, + [CLK_FANOUT1] = &fanout1_clk.common.hw, + [CLK_FANOUT2] = &fanout2_clk.common.hw, + [CLK_FANOUT3] = &fanout3_clk.common.hw, }, .num = CLK_FANOUT3 + 1, }; From patchwork Fri Oct 9 15:52:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3586 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4]) by mxe881.netcup.net (Postfix) with ESMTPS id 104261C1D2D for ; Fri, 9 Oct 2026 18:09:24 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 104.64.211.4) smtp.mailfrom=linux-sunxi+bounces-26573-noreply=patchwork.local@lists.linux.dev smtp.helo=sin.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 104.64.211.4 as permitted sender) client-ip=104.64.211.4; envelope-from=linux-sunxi+bounces-26573-noreply=patchwork.local@lists.linux.dev; helo=sin.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sin.lore.kernel.org (Postfix) with ESMTP id E9F0B2F20E for ; Fri, 9 Oct 2026 15:55:13 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CAB383911C5; Fri, 9 Oct 2026 15:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="M4aoYizR" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9561A35F5E4 for ; Fri, 9 Oct 2026 15:54:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.180.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561281; cv=pass; b=uZTvr0WdgcMYb+l606tP5HSfk99AGFlewpgUaiVOgf5+VPjzcJHi2Rv8NIXGJ5fbmgjvwLOr8g1ReflHcyhWmoblavNgO8MSpvM79NIcAJ/UFtCnaShCqRduTL/UST4cA+Q78eY9zTrOo2Y29Ypn03IUFXU7o8HlcyqlL5LkZ40= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561281; c=relaxed/simple; bh=Ri6+g/LnZ55vNID1HFEMQHaHeNa6lcaELkI3GrmYLEw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IZcIQg9LGE+8LgVAegB6Mrl/1HSSkkX56AMkk+i95yTWKe58Us/KZn2/btLrMGDqb/V982QUpn5lnLZw3XlJ80y0OIbj40iIy62vhP1EqEPfM1lJXMD3EeSCocroqoCByChn5cjoifoEJO6sQidzTDtk8FUUv0/z3IGuAaevOJA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=M4aoYizR; arc=pass smtp.client-ip=165.173.180.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561252; cv=none; d=zohomail.com; s=zohoarc; b=DWeA+x6zfWQSC987rIdeggpBl5zP4YbonUl7V8UZ1ljqaQ463T9M4mRIX68yE27/k7eOvmrxowQgD64oWENuNN4vgGPzCYTM7avoYV3zN/PV1KL5zLqcCM+j17BpKD6aUgxcUhWObBpZWC1jT+B8CxMUM68EMZM1TxqepvGb9ZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561252; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=e9Zbrp8PeAEz+fRzrBYgUZtPM98eSE+SZRnfvcLJE1M=; b=mxDs/HfP2RUQiSYKZk+FDByifE2jDEnXSVpEtz5dUL1vvCznKuLWVeZHXGIu5oRyK5KTYzzEzgH3fGC93TrYy8lSmcO/xL1uXh9k28THhMgUYobLyZLNzKx6oYauZOZo/8g9EsPDKr+mQXegmJ5kDZcWmxvfHe4PgUYfEFXdey0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561252; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=e9Zbrp8PeAEz+fRzrBYgUZtPM98eSE+SZRnfvcLJE1M=; b=M4aoYizRL5wwTSbRGt0boeZ6d9Ebs9nH2FjFA/DWF/2I1pHSUDGCvmDSbgjdcjx2 NnXfBL1WHYXpbJpB2Tvbq/1d0QidVg7X4fRfPKEN8+lPzFAwAPTYNawr+hv9uBcZC9Z vKb3Q/sdgxD5DvFN+C2tkJY706CqdElDZiyAqNew= Received: by smtp.zohomail.com with SMTPS id 1791561252145282.7718686023061; Fri, 9 Oct 2026 08:54:12 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:12 +0800 Subject: [PATCH v6 7/8] clk: sunxi-ng: a733: Add bus clock gates Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-7-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=44341; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=Ri6+g/LnZ55vNID1HFEMQHaHeNa6lcaELkI3GrmYLEw=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8p5lzuv98LLG4Zd7loTqJ2++FZqKky9/i/258gKDT LKFIe+OjlIWBjEuBlkxRRYuf/F/1jo8344ItN6HmcPKBDKEgYtTACaSqsPwV2LiWz/nKdGL+y7v /HJ16YO/M+x9sj0y1xzIOyFcbPv5jS7D/6wYeRmnjSs++kq+5Jcxb2GUf8eqvvxghejxBN0LO3h CeAA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-2.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[104.64.211.4:from]; SUSPICIOUS_RECIPS(1.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWELVE(0.00)[28]; TAGGED_RCPT(0.00)[clk,dt]; PRECEDENCE_BULK(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; DMARC_NA(0.00)[pigmoral.tech]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,baylibre.com,gmail.com,arm.com,proton.me]; DBL_BLOCKED_OPENRESOLVER(0.00)[baylibre.com:email,pigmoral.tech:email,pigmoral.tech:dkim,arm.com:email]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=2]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[165.173.180.15:received,100.90.174.1:received]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[pigmoral.tech:s=zmail]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org,pengutronix.de,pigmoral.tech,dabbelt.com,eecs.berkeley.edu,ghiti.fr]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; DKIM_TRACE(0.00)[pigmoral.tech:+]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:104.64.211.4]; RCVD_COUNT_FIVE(0.00)[5]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FROM_NEQ_ENVFROM(0.00)[junhui.liu@pigmoral.tech,linux-sunxi@lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:63949, ipnet:104.64.192.0/19, country:SG]; TAGGED_FROM(0.00)[bounces-26573-noreply=patchwork.local]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[104.64.211.4:from] X-Rspamd-Queue-Id: 104261C1D2D X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add the bus clock gates that control access to the devices' register interface on the Allwinner A733 SoC. These clocks are typically single-bit controls in the BGR registers, covering UARTs, SPI, I2C, and various multimedia engines. It also includes bus gates for system components like the IOMMU and MSI-lite interfaces. Also mark the ahb-store, mbus-store and ahb-cpus clocks as critical. Disabling either store gate breaks access to boot/storage devices such as MMC and SPI NOR, while gating ahb-cpus hangs any access to the CPUS power domain registers when unused clocks are disabled. Tested-by: Jerome Brunet Reviewed-by: Andre Przywara Reviewed-by: Chen-Yu Tsai Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 501 ++++++++++++++++++++++++++++++++- 1 file changed, 500 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c index 7847eec84313..c26b640fd257 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -11,6 +11,10 @@ * * CPU_PERI_CLK_REG has no documented consumer, while NSI_CLK_REG has no * known kernel consumer, so they are not modelled here. + * + * TODO: The real parents of some bus gates, including its-pcie0-aclk, + * msi-lite, npu, sgpio, lpc and i2spcm, are not documented in the + * manual. For now, follow the vendor BSP, which keeps them on hosc. */ #include @@ -454,16 +458,19 @@ static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500, 0, 5, /* M */ 24, 2, /* mux */ 0); +static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw }; static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, 0, 5, /* M */ 24, 2, /* mux */ 0); +static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw }; static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, 0, 5, /* M */ 24, 2, /* mux */ 0); +static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw }; static const struct clk_parent_data apb_uart_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -476,6 +483,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x5 0, 5, /* M */ 24, 3, /* mux */ 0); +static const struct clk_hw *apb_uart_hws[] = { + &apb_uart_clk.common.hw +}; static const struct clk_parent_data trace_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -503,6 +513,8 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gic_clk, "gic", gic_parents, 0x560, BIT(31), /* gate */ CLK_IS_CRITICAL); +static SUNXI_CCU_GATE_DATA(bus_its_pcie0_aclk_clk, "bus-its-pcie0-aclk", hosc, 0x574, BIT(1), 0); + static const struct clk_parent_data mbus_parents[] = { { .hw = &sys_24M_clk.hw }, { .hw = &pll_periph1_600M_clk.hw }, @@ -517,9 +529,127 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588 BIT(31), /* gate */ CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); +static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw }; + +static SUNXI_CCU_GATE_HWS(mbus_iommu0_sys_clk, "mbus-iommu0-sys", mbus_hws, 0x58c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu0_sys_clk, "apb-iommu0-sys", apb0_hws, 0x58c, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu0_sys_clk, "ahb-iommu0-sys", ahb_hws, 0x58c, BIT(2), 0); + +static SUNXI_CCU_GATE_DATA(bus_msi_lite0_clk, "bus-msi-lite0", hosc, 0x594, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_msi_lite1_clk, "bus-msi-lite1", hosc, 0x59c, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_msi_lite2_clk, "bus-msi-lite2", hosc, 0x5a4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, "mbus-iommu1-sys", mbus_hws, 0x5b4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, "apb-iommu1-sys", apb0_hws, 0x5b4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, "ahb-iommu1-sys", ahb_hws, 0x5b4, BIT(2), 0); + +static SUNXI_CCU_GATE_HWS(ahb_ve_dec_clk, "ahb-ve-dec", ahb_hws, + 0x5c0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(ahb_ve_enc_clk, "ahb-ve-enc", ahb_hws, + 0x5c0, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_in_clk, "ahb-vid-in", ahb_hws, + 0x5c0, BIT(2), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_cout0_clk, "ahb-vid-cout0", ahb_hws, + 0x5c0, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_cout1_clk, "ahb-vid-cout1", ahb_hws, + 0x5c0, BIT(4), 0); +static SUNXI_CCU_GATE_HWS(ahb_de_clk, "ahb-de", ahb_hws, + 0x5c0, BIT(5), 0); +static SUNXI_CCU_GATE_HWS(ahb_npu_clk, "ahb-npu", ahb_hws, + 0x5c0, BIT(6), 0); +static SUNXI_CCU_GATE_HWS(ahb_gpu0_clk, "ahb-gpu0", ahb_hws, + 0x5c0, BIT(7), 0); +static SUNXI_CCU_GATE_HWS(ahb_serdes_clk, "ahb-serdes", ahb_hws, + 0x5c0, BIT(8), 0); +static SUNXI_CCU_GATE_HWS(ahb_usb_sys_clk, "ahb-usb-sys", ahb_hws, + 0x5c0, BIT(9), 0); +static SUNXI_CCU_GATE_HWS(ahb_msi_lite0_clk, "ahb-msi-lite0", ahb_hws, + 0x5c0, BIT(16), 0); + +/* This gate controls access to the storage controller MMIO registers. */ +static SUNXI_CCU_GATE_HWS(ahb_store_clk, "ahb-store", ahb_hws, + 0x5c0, BIT(24), 0); +static const struct clk_hw *ahb_store_hws[] = { &ahb_store_clk.common.hw }; + +/* Keep enabled for access to the CPUS domain registers. */ +static SUNXI_CCU_GATE_HWS(ahb_cpus_clk, "ahb-cpus", ahb_hws, + 0x5c0, BIT(28), CLK_IS_CRITICAL); + +static SUNXI_CCU_GATE_HWS(mbus_iommu0_clk, "mbus-iommu0", mbus_hws, + 0x5e0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(mbus_iommu1_clk, "mbus-iommu1", mbus_hws, + 0x5e0, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(mbus_desys_clk, "mbus-desys", mbus_hws, + 0x5e0, BIT(11), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_gate_clk, "mbus-ve-enc0-gate", mbus_hws, + 0x5e0, BIT(12), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_gate_clk, "mbus-ve-dec0-gate", mbus_hws, + 0x5e0, BIT(14), 0); +static SUNXI_CCU_GATE_HWS(mbus_gpu0_clk, "mbus-gpu0", mbus_hws, + 0x5e0, BIT(16), 0); +static SUNXI_CCU_GATE_HWS(mbus_npu_clk, "mbus-npu", mbus_hws, + 0x5e0, BIT(18), 0); +static SUNXI_CCU_GATE_HWS(mbus_vid_in_clk, "mbus-vid-in", mbus_hws, + 0x5e0, BIT(24), 0); +static SUNXI_CCU_GATE_HWS(mbus_serdes_clk, "mbus-serdes", mbus_hws, + 0x5e0, BIT(28), 0); +static SUNXI_CCU_GATE_HWS(mbus_msi_lite0_clk, "mbus-msi-lite0", mbus_hws, + 0x5e0, BIT(29), 0); + +/* Keep enabled for the storage controller DMA paths. */ +static SUNXI_CCU_GATE_HWS(mbus_store_clk, "mbus-store", mbus_hws, + 0x5e0, BIT(30), CLK_IS_CRITICAL); +static const struct clk_hw *mbus_store_hws[] = { &mbus_store_clk.common.hw }; + +static SUNXI_CCU_GATE_HWS(mbus_msi_lite2_clk, "mbus-msi-lite2", mbus_hws, + 0x5e0, BIT(31), 0); + +static SUNXI_CCU_GATE_HWS(mbus_dma0_clk, "mbus-dma0", mbus_hws, + 0x5e4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_clk, "mbus-ve-enc0", mbus_hws, + 0x5e4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws, + 0x5e4, BIT(2), 0); +static SUNXI_CCU_GATE_HWS(mbus_dma1_clk, "mbus-dma1", mbus_hws, + 0x5e4, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(mbus_nand0_clk, "mbus-nand0", mbus_store_hws, + 0x5e4, BIT(5), 0); +static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws, + 0x5e4, BIT(8), 0); +static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws, + 0x5e4, BIT(9), 0); +static SUNXI_CCU_GATE_HWS(mbus_gmac0_clk, "mbus-gmac0", mbus_hws, + 0x5e4, BIT(11), 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws, + 0x5e4, BIT(12), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_clk, "mbus-ve-dec0", mbus_hws, + 0x5e4, BIT(18), 0); + +static SUNXI_CCU_GATE_HWS(bus_dma0_clk, "bus-dma0", ahb_hws, + 0x704, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_dma1_clk, "bus-dma1", ahb_hws, + 0x70c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, + 0x724, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws, + 0x744, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb0_hws, + 0x784, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb0_hws, + 0x78c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", sys_24M_hws, + 0x7a4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, + 0x7ac, BIT(0), 0); /************************************************************************** - * mod clocks * + * mod clocks with gates * **************************************************************************/ static const struct clk_parent_data timer_parents[] = { @@ -579,6 +709,7 @@ static SUNXI_CCU_P_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents, 0x824 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_timer_clk, "bus-timer", ahb_hws, 0x850, BIT(0), 0); /* Undocumented, taken from the vendor kernel. */ static const struct clk_parent_data avs_parents[] = { @@ -604,6 +735,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(de0_clk, "de0", de_parents, 0xa00, 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_de0_clk, "bus-de0", ahb_hws, 0xa04, BIT(0), 0); static const struct clk_hw *di_parents[] = { &pll_periph0_600M_clk.hw, @@ -617,6 +749,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20, 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0xa24, BIT(0), 0); static const struct clk_hw *g2d_parents[] = { &pll_periph0_400M_clk.hw, @@ -629,6 +762,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40, 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0xa44, BIT(0), 0); static const struct clk_hw *eink_parents[] = { &pll_periph0_480M_clk.common.hw, @@ -652,6 +786,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_panel_par 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_eink_clk, "bus-eink", ahb_hws, 0xa6c, BIT(0), 0); static const struct clk_hw *ve_enc_parents[] = { &pll_ve0_clk.common.hw, @@ -683,6 +818,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec0_clk, "ve-dec0", ve_dec_parents, 0xa8 BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_ve_enc0_clk, "bus-ve-enc0", ahb_hws, 0xa8c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ve_dec0_clk, "bus-ve-dec0", ahb_hws, 0xa8c, BIT(2), 0); + static const struct clk_hw *ce_parents[] = { &sys_24M_clk.hw, &pll_periph0_400M_clk.hw, @@ -693,6 +831,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0xac4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0xac4, BIT(1), 0); static const struct clk_hw *npu_parents[] = { &pll_npu_clk.common.hw, @@ -708,6 +848,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_npu_clk, "bus-npu", hosc, 0xb04, BIT(0), 0); /* * GPU_CLK = ClockSource * ((16 - M) / 16) @@ -740,6 +881,7 @@ static struct ccu_div gpu0_clk = { &ccu_div_ops, 0), } }; +static SUNXI_CCU_GATE_HWS(bus_gpu0_clk, "bus-gpu0", ahb_hws, 0xb24, BIT(0), 0); static const struct clk_parent_data dram_parents[] = { { .hw = &pll_ddr_clk.common.hw, }, @@ -754,6 +896,8 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc BIT(31), /* gate */ CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_GATE_HWS(bus_dram0_clk, "bus-dram0", ahb_hws, 0xc0c, + BIT(0), CLK_IS_CRITICAL); static const struct clk_parent_data nand_mmc_parents[] = { { .hw = &sys_24M_clk.hw, }, @@ -772,6 +916,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk1_clk, "nand0-clk1", nand_mmc_par 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_nand0_clk, "bus-nand0", ahb_store_hws, 0xc8c, BIT(0), 0); static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, 0xd00, 0, 5, /* M */ @@ -780,6 +925,8 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, BIT(31), /* gate */ 2, /* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_store_hws, 0xd0c, BIT(0), 0); + static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, 0xd10, 0, 5, /* M */ 8, 5, /* P */ @@ -787,6 +934,7 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, BIT(31), /* gate */ 2, /* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_store_hws, 0xd1c, BIT(0), 0); static const struct clk_parent_data mmc2_mmc3_parents[] = { { .hw = &sys_24M_clk.hw, }, @@ -802,6 +950,8 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_parents BIT(31), /* gate */ 2, /* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_store_hws, 0xd2c, BIT(0), 0); + static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parents, 0xd30, 0, 5, /* M */ 8, 5, /* P */ @@ -809,6 +959,7 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parents BIT(31), /* gate */ 2, /* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc3_clk, "bus-mmc3", ahb_store_hws, 0xd3c, BIT(0), 0); static const struct clk_hw *ufs_axi_parents[] = { &pll_periph0_300M_clk.hw, @@ -829,6 +980,29 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_parents, 0 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ufs_clk, "bus-ufs", ahb_store_hws, 0xd8c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb_uart_hws, 0xe00, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb_uart_hws, 0xe04, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb_uart_hws, 0xe08, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb_uart_hws, 0xe0c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb_uart_hws, 0xe10, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb_uart_hws, 0xe14, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb_uart_hws, 0xe18, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0xe80, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0xe84, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0xe88, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0xe8c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0xe90, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0xe94, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c6_clk, "bus-i2c6", apb1_hws, 0xe98, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c7_clk, "bus-i2c7", apb1_hws, 0xe9c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c8_clk, "bus-i2c8", apb1_hws, 0xea0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c9_clk, "bus-i2c9", apb1_hws, 0xea4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c10_clk, "bus-i2c10", apb1_hws, 0xea8, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c11_clk, "bus-i2c11", apb1_hws, 0xeac, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c12_clk, "bus-i2c12", apb1_hws, 0xeb0, BIT(0), 0); static const struct clk_parent_data spi_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -846,18 +1020,23 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_store_hws, 0xf04, BIT(0), 0); + static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0xf08, 0, 5, /* M */ 8, 5, /* N */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_store_hws, 0xf0c, BIT(0), 0); + static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0xf10, 0, 5, /* M */ 8, 5, /* N */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_store_hws, 0xf14, BIT(0), 0); static const struct clk_parent_data spif_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -875,12 +1054,16 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_store_hws, 0xf1c, BIT(0), 0); + static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, "spi3", spi_parents, 0xf20, 0, 5, /* M */ 8, 5, /* N */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_store_hws, 0xf24, BIT(0), 0); + /* Undocumented, taken from the vendor kernel. */ static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, 0, 5, /* M */ @@ -888,6 +1071,7 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi4_clk, "bus-spi4", ahb_store_hws, 0xf2c, BIT(0), 0); static const struct clk_parent_data gpadc0_24m_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -898,6 +1082,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc0_24m_clk, "gpadc0-24m", gpadc0_24m_p 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0xfc4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_ths0_clk, "bus-ths0", apb0_hws, 0xfe4, BIT(0), 0); static const struct clk_parent_data irrx_parents[] = { { .fw_name = "losc"}, @@ -909,6 +1096,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x1000, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_irrx_clk, "bus-irrx", apb0_hws, 0x1004, BIT(0), 0); static const struct clk_parent_data irtx_parents[] = { { .fw_name = "losc"}, @@ -920,6 +1108,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x1008, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_irtx_clk, "bus-irtx", apb0_hws, 0x100c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0x1024, BIT(0), 0); /* Undocumented, taken from the vendor kernel. */ static const struct clk_parent_data sgpio_parents[] = { @@ -931,6 +1122,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0x1060, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_sgpio_clk, "bus-sgpio", hosc, 0x1064, BIT(0), 0); /* Undocumented, taken from the vendor kernel. */ static const struct clk_hw *lpc_parents[] = { @@ -944,6 +1136,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_lpc_clk, "bus-lpc", hosc, 0x1084, BIT(0), 0); static const struct clk_hw *i2spcm_parents[] = { &pll_audio0_4x_clk.common.hw, @@ -956,11 +1149,15 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents, 0x12 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm0_clk, "bus-i2spcm0", hosc, 0x120c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, "i2spcm1", i2spcm_parents, 0x1210, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm1_clk, "bus-i2spcm1", hosc, 0x121c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents, 0x1220, 0, 5, /* M */ 24, 3, /* mux */ @@ -979,16 +1176,22 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2spcm2_as 24, 3, /* mux */ BIT(31), /* gate */ 0); + +static SUNXI_CCU_GATE_DATA(bus_i2spcm2_clk, "bus-i2spcm2", hosc, 0x122c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents, 0x1230, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm3_clk, "bus-i2spcm3", hosc, 0x123c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents, 0x1240, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm4_clk, "bus-i2spcm4", hosc, 0x124c, BIT(0), 0); static const struct clk_hw *spdif_tx_parents[] = { &pll_audio0_4x_clk.common.hw, @@ -1012,6 +1215,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb1_hws, 0x128c, BIT(0), 0); + static const struct clk_hw *dmic_parents[] = { &pll_audio0_4x_clk.common.hw, &pll_audio1_div2_clk.hw, @@ -1023,6 +1228,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0, BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb1_hws, 0x12cc, BIT(0), 0); + /* * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also used by @@ -1054,6 +1261,9 @@ static struct ccu_mux usb_ohci0_clk = { &ccu_mux_ops, 0), }, }; +static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0x1304, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0x1304, BIT(4), 0); +static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0x1304, BIT(8), 0); static struct ccu_mux usb_ohci1_clk = { .enable = BIT(31), @@ -1070,6 +1280,8 @@ static struct ccu_mux usb_ohci1_clk = { &ccu_mux_ops, 0), }, }; +static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0x130c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0x130c, BIT(4), 0); static const struct clk_parent_data usb01_ref_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -1172,11 +1384,14 @@ static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_150M_hw 0, 5, /* M */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gmac0_clk, "bus-gmac0", ahb_hws, 0x141c, BIT(0), 0); + /* Undocumented, taken from the vendor kernel. */ static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac1-phy", pll_periph0_150M_hws, 0x1420, 0, 5, /* M */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gmac1_clk, "bus-gmac1", ahb_hws, 0x142c, BIT(0), 0); static const struct clk_hw *tcon_lcd_parents[] = { &pll_video0_4x_clk.common.hw, @@ -1189,17 +1404,22 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_parents 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0x1504, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_parents, 0x1508, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0x150c, BIT(0), 0); + /* Undocumented, taken from the vendor kernel. */ static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", tcon_lcd_parents, 0x1510, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0x1514, BIT(0), 0); static const struct clk_hw *dsi_parents[] = { &sys_24M_clk.hw, @@ -1211,11 +1431,14 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dsi0_clk, "bus-dsi0", ahb_hws, 0x1584, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588, 0, 5, /* M */ 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dsi1_clk, "bus-dsi1", ahb_hws, 0x158c, BIT(0), 0); static const struct clk_hw *combphy_parents[] = { &pll_video0_4x_clk.common.hw, @@ -1235,6 +1458,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_parents, 0 BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0x1604, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0x160c, BIT(0), 0); + static const struct clk_hw *edp_tv_parents[] = { &pll_video0_4x_clk.common.hw, &pll_video1_4x_clk.common.hw, @@ -1246,6 +1472,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, 0x1640 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_edp_tv_clk, "bus-edp-tv", ahb_hws, 0x164c, BIT(0), 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pll_periph0_2x_hws, 0x1680, BIT(30), /* gate */ @@ -1273,6 +1500,7 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents, 0x168 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_hdmi_tv_clk, "bus-hdmi-tv", ahb_hws, 0x168c, BIT(0), 0); static const struct clk_parent_data hdmi_sfr_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -1285,6 +1513,9 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_parents, static SUNXI_CCU_GATE_HWS(hdcp_esm_clk, "hdcp-esm", pll_periph0_300M_hws, 0x1694, BIT(31), 0); +static SUNXI_CCU_GATE_HWS(bus_dpss_top0_clk, "bus-dpss-top0", ahb_hws, 0x16c4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_dpss_top1_clk, "bus-dpss-top1", ahb_hws, 0x16cc, BIT(0), 0); + static const struct clk_parent_data ledc_parents[] = { { .hw = &sys_24M_clk.hw }, { .hw = &pll_periph0_600M_clk.hw }, @@ -1295,6 +1526,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x1700, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0x1704, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_dsc_clk, "bus-dsc", ahb_hws, 0x1744, BIT(0), 0); static const struct clk_parent_data csi_master_parents[] = { { .hw = &sys_24M_clk.hw }, @@ -1336,6 +1570,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0x1844, BIT(0), 0); static const struct clk_hw *isp_parents[] = { &pll_video2_4x_clk.common.hw, @@ -1464,7 +1699,60 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &apb_uart_clk.common, &trace_clk.common, &gic_clk.common, + &bus_its_pcie0_aclk_clk.common, &mbus_clk.common, + &mbus_iommu0_sys_clk.common, + &apb_iommu0_sys_clk.common, + &ahb_iommu0_sys_clk.common, + &bus_msi_lite0_clk.common, + &bus_msi_lite1_clk.common, + &bus_msi_lite2_clk.common, + &mbus_iommu1_sys_clk.common, + &apb_iommu1_sys_clk.common, + &ahb_iommu1_sys_clk.common, + &ahb_ve_dec_clk.common, + &ahb_ve_enc_clk.common, + &ahb_vid_in_clk.common, + &ahb_vid_cout0_clk.common, + &ahb_vid_cout1_clk.common, + &ahb_de_clk.common, + &ahb_npu_clk.common, + &ahb_gpu0_clk.common, + &ahb_serdes_clk.common, + &ahb_usb_sys_clk.common, + &ahb_msi_lite0_clk.common, + &ahb_store_clk.common, + &ahb_cpus_clk.common, + &mbus_iommu0_clk.common, + &mbus_iommu1_clk.common, + &mbus_desys_clk.common, + &mbus_ve_enc0_gate_clk.common, + &mbus_ve_dec0_gate_clk.common, + &mbus_gpu0_clk.common, + &mbus_npu_clk.common, + &mbus_vid_in_clk.common, + &mbus_serdes_clk.common, + &mbus_msi_lite0_clk.common, + &mbus_store_clk.common, + &mbus_msi_lite2_clk.common, + &mbus_dma0_clk.common, + &mbus_ve_enc0_clk.common, + &mbus_ce_clk.common, + &mbus_dma1_clk.common, + &mbus_nand0_clk.common, + &mbus_csi_clk.common, + &mbus_isp_clk.common, + &mbus_gmac0_clk.common, + &mbus_gmac1_clk.common, + &mbus_ve_dec0_clk.common, + &bus_dma0_clk.common, + &bus_dma1_clk.common, + &bus_spinlock_clk.common, + &bus_msgbox0_clk.common, + &bus_pwm0_clk.common, + &bus_pwm1_clk.common, + &bus_dbg_clk.common, + &bus_sysdap_clk.common, &timer0_clk.common, &timer1_clk.common, &timer2_clk.common, @@ -1475,48 +1763,111 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &timer7_clk.common, &timer8_clk.common, &timer9_clk.common, + &bus_timer_clk.common, &avs_clk.common, &de0_clk.common, + &bus_de0_clk.common, &di_clk.common, + &bus_di_clk.common, &g2d_clk.common, + &bus_g2d_clk.common, &eink_clk.common, &eink_panel_clk.common, + &bus_eink_clk.common, &ve_enc0_clk.common, &ve_dec0_clk.common, + &bus_ve_enc0_clk.common, + &bus_ve_dec0_clk.common, &ce_clk.common, + &bus_ce_clk.common, + &bus_ce_sys_clk.common, &npu_clk.common, + &bus_npu_clk.common, &gpu0_clk.common, + &bus_gpu0_clk.common, &dram0_clk.common, + &bus_dram0_clk.common, &nand0_clk0_clk.common, &nand0_clk1_clk.common, + &bus_nand0_clk.common, &mmc0_clk.common, + &bus_mmc0_clk.common, &mmc1_clk.common, + &bus_mmc1_clk.common, &mmc2_clk.common, + &bus_mmc2_clk.common, &mmc3_clk.common, + &bus_mmc3_clk.common, &ufs_axi_clk.common, &ufs_cfg_clk.common, + &bus_ufs_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_uart5_clk.common, + &bus_uart6_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_i2c3_clk.common, + &bus_i2c4_clk.common, + &bus_i2c5_clk.common, + &bus_i2c6_clk.common, + &bus_i2c7_clk.common, + &bus_i2c8_clk.common, + &bus_i2c9_clk.common, + &bus_i2c10_clk.common, + &bus_i2c11_clk.common, + &bus_i2c12_clk.common, &spi0_clk.common, + &bus_spi0_clk.common, &spi1_clk.common, + &bus_spi1_clk.common, &spi2_clk.common, + &bus_spi2_clk.common, &spif_clk.common, + &bus_spif_clk.common, &spi3_clk.common, + &bus_spi3_clk.common, &spi4_clk.common, + &bus_spi4_clk.common, &gpadc0_24m_clk.common, + &bus_gpadc0_clk.common, + &bus_ths0_clk.common, &irrx_clk.common, + &bus_irrx_clk.common, &irtx_clk.common, + &bus_irtx_clk.common, + &bus_lradc_clk.common, &sgpio_clk.common, + &bus_sgpio_clk.common, &lpc_clk.common, + &bus_lpc_clk.common, &i2spcm0_clk.common, + &bus_i2spcm0_clk.common, &i2spcm1_clk.common, + &bus_i2spcm1_clk.common, &i2spcm2_clk.common, &i2spcm2_asrc_clk.common, + &bus_i2spcm2_clk.common, &i2spcm3_clk.common, + &bus_i2spcm3_clk.common, &i2spcm4_clk.common, + &bus_i2spcm4_clk.common, &spdif_tx_clk.common, &spdif_rx_clk.common, + &bus_spdif_clk.common, &dmic_clk.common, + &bus_dmic_clk.common, &usb_ohci0_clk.common, + &bus_ohci0_clk.common, + &bus_ehci0_clk.common, + &bus_otg_clk.common, &usb_ohci1_clk.common, + &bus_ohci1_clk.common, + &bus_ehci1_clk.common, &usb01_ref_clk.common, &usb2_u2_ref_clk.common, &usb2_suspend_clk.common, @@ -1528,25 +1879,41 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &serdes_phy_clk.common, &gmac_ptp_clk.common, &gmac0_phy_clk.common, + &bus_gmac0_clk.common, &gmac1_phy_clk.common, + &bus_gmac1_clk.common, &tcon_lcd0_clk.common, + &bus_tcon_lcd0_clk.common, &tcon_lcd1_clk.common, + &bus_tcon_lcd1_clk.common, &tcon_lcd2_clk.common, + &bus_tcon_lcd2_clk.common, &dsi0_clk.common, + &bus_dsi0_clk.common, &dsi1_clk.common, + &bus_dsi1_clk.common, &combphy0_clk.common, &combphy1_clk.common, + &bus_tcon_tv0_clk.common, + &bus_tcon_tv1_clk.common, &edp_tv_clk.common, + &bus_edp_tv_clk.common, &hdmi_cec_32k_clk.common, &hdmi_cec_clk.common, &hdmi_tv_clk.common, + &bus_hdmi_tv_clk.common, &hdmi_sfr_clk.common, &hdcp_esm_clk.common, + &bus_dpss_top0_clk.common, + &bus_dpss_top1_clk.common, &ledc_clk.common, + &bus_ledc_clk.common, + &bus_dsc_clk.common, &csi_master0_clk.common, &csi_master1_clk.common, &csi_master2_clk.common, &csi_clk.common, + &bus_csi_clk.common, &isp_clk.common, &res_dcap_24m_clk.common, &apb2jtag_clk.common, @@ -1613,7 +1980,60 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_APB_UART] = &apb_uart_clk.common.hw, [CLK_TRACE] = &trace_clk.common.hw, [CLK_GIC] = &gic_clk.common.hw, + [CLK_BUS_ITS_PCIE0_ACLK] = &bus_its_pcie0_aclk_clk.common.hw, [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_MBUS_IOMMU0_SYS] = &mbus_iommu0_sys_clk.common.hw, + [CLK_APB_IOMMU0_SYS] = &apb_iommu0_sys_clk.common.hw, + [CLK_AHB_IOMMU0_SYS] = &ahb_iommu0_sys_clk.common.hw, + [CLK_BUS_MSI_LITE0] = &bus_msi_lite0_clk.common.hw, + [CLK_BUS_MSI_LITE1] = &bus_msi_lite1_clk.common.hw, + [CLK_BUS_MSI_LITE2] = &bus_msi_lite2_clk.common.hw, + [CLK_MBUS_IOMMU1_SYS] = &mbus_iommu1_sys_clk.common.hw, + [CLK_APB_IOMMU1_SYS] = &apb_iommu1_sys_clk.common.hw, + [CLK_AHB_IOMMU1_SYS] = &ahb_iommu1_sys_clk.common.hw, + [CLK_AHB_VE_DEC] = &ahb_ve_dec_clk.common.hw, + [CLK_AHB_VE_ENC] = &ahb_ve_enc_clk.common.hw, + [CLK_AHB_VID_IN] = &ahb_vid_in_clk.common.hw, + [CLK_AHB_VID_COUT0] = &ahb_vid_cout0_clk.common.hw, + [CLK_AHB_VID_COUT1] = &ahb_vid_cout1_clk.common.hw, + [CLK_AHB_DE] = &ahb_de_clk.common.hw, + [CLK_AHB_NPU] = &ahb_npu_clk.common.hw, + [CLK_AHB_GPU0] = &ahb_gpu0_clk.common.hw, + [CLK_AHB_SERDES] = &ahb_serdes_clk.common.hw, + [CLK_AHB_USB_SYS] = &ahb_usb_sys_clk.common.hw, + [CLK_AHB_MSI_LITE0] = &ahb_msi_lite0_clk.common.hw, + [CLK_AHB_STORE] = &ahb_store_clk.common.hw, + [CLK_AHB_CPUS] = &ahb_cpus_clk.common.hw, + [CLK_MBUS_IOMMU0] = &mbus_iommu0_clk.common.hw, + [CLK_MBUS_IOMMU1] = &mbus_iommu1_clk.common.hw, + [CLK_MBUS_DESYS] = &mbus_desys_clk.common.hw, + [CLK_MBUS_VE_ENC0_GATE] = &mbus_ve_enc0_gate_clk.common.hw, + [CLK_MBUS_VE_DEC0_GATE] = &mbus_ve_dec0_gate_clk.common.hw, + [CLK_MBUS_GPU0] = &mbus_gpu0_clk.common.hw, + [CLK_MBUS_NPU] = &mbus_npu_clk.common.hw, + [CLK_MBUS_VID_IN] = &mbus_vid_in_clk.common.hw, + [CLK_MBUS_SERDES] = &mbus_serdes_clk.common.hw, + [CLK_MBUS_MSI_LITE0] = &mbus_msi_lite0_clk.common.hw, + [CLK_MBUS_STORE] = &mbus_store_clk.common.hw, + [CLK_MBUS_MSI_LITE2] = &mbus_msi_lite2_clk.common.hw, + [CLK_MBUS_DMA0] = &mbus_dma0_clk.common.hw, + [CLK_MBUS_VE_ENC0] = &mbus_ve_enc0_clk.common.hw, + [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, + [CLK_MBUS_DMA1] = &mbus_dma1_clk.common.hw, + [CLK_MBUS_NAND0] = &mbus_nand0_clk.common.hw, + [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw, + [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw, + [CLK_MBUS_GMAC0] = &mbus_gmac0_clk.common.hw, + [CLK_MBUS_GMAC1] = &mbus_gmac1_clk.common.hw, + [CLK_MBUS_VE_DEC0] = &mbus_ve_dec0_clk.common.hw, + [CLK_BUS_DMA0] = &bus_dma0_clk.common.hw, + [CLK_BUS_DMA1] = &bus_dma1_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw, + [CLK_BUS_PWM0] = &bus_pwm0_clk.common.hw, + [CLK_BUS_PWM1] = &bus_pwm1_clk.common.hw, + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, + [CLK_BUS_SYSDAP] = &bus_sysdap_clk.common.hw, [CLK_TIMER0] = &timer0_clk.common.hw, [CLK_TIMER1] = &timer1_clk.common.hw, [CLK_TIMER2] = &timer2_clk.common.hw, @@ -1624,48 +2044,111 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_TIMER7] = &timer7_clk.common.hw, [CLK_TIMER8] = &timer8_clk.common.hw, [CLK_TIMER9] = &timer9_clk.common.hw, + [CLK_BUS_TIMER] = &bus_timer_clk.common.hw, [CLK_AVS] = &avs_clk.common.hw, [CLK_DE0] = &de0_clk.common.hw, + [CLK_BUS_DE0] = &bus_de0_clk.common.hw, [CLK_DI] = &di_clk.common.hw, + [CLK_BUS_DI] = &bus_di_clk.common.hw, [CLK_G2D] = &g2d_clk.common.hw, + [CLK_BUS_G2D] = &bus_g2d_clk.common.hw, [CLK_EINK] = &eink_clk.common.hw, [CLK_EINK_PANEL] = &eink_panel_clk.common.hw, + [CLK_BUS_EINK] = &bus_eink_clk.common.hw, [CLK_VE_ENC0] = &ve_enc0_clk.common.hw, [CLK_VE_DEC0] = &ve_dec0_clk.common.hw, + [CLK_BUS_VE_ENC0] = &bus_ve_enc0_clk.common.hw, + [CLK_BUS_VE_DEC0] = &bus_ve_dec0_clk.common.hw, [CLK_CE] = &ce_clk.common.hw, + [CLK_BUS_CE] = &bus_ce_clk.common.hw, + [CLK_BUS_CE_SYS] = &bus_ce_sys_clk.common.hw, [CLK_NPU] = &npu_clk.common.hw, + [CLK_BUS_NPU] = &bus_npu_clk.common.hw, [CLK_GPU0] = &gpu0_clk.common.hw, + [CLK_BUS_GPU0] = &bus_gpu0_clk.common.hw, [CLK_DRAM0] = &dram0_clk.common.hw, + [CLK_BUS_DRAM0] = &bus_dram0_clk.common.hw, [CLK_NAND0_CLK0] = &nand0_clk0_clk.common.hw, [CLK_NAND0_CLK1] = &nand0_clk1_clk.common.hw, + [CLK_BUS_NAND0] = &bus_nand0_clk.common.hw, [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw, [CLK_UFS_AXI] = &ufs_axi_clk.common.hw, [CLK_UFS_CFG] = &ufs_cfg_clk.common.hw, + [CLK_BUS_UFS] = &bus_ufs_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, + [CLK_BUS_UART6] = &bus_uart6_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, + [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, + [CLK_BUS_I2C5] = &bus_i2c5_clk.common.hw, + [CLK_BUS_I2C6] = &bus_i2c6_clk.common.hw, + [CLK_BUS_I2C7] = &bus_i2c7_clk.common.hw, + [CLK_BUS_I2C8] = &bus_i2c8_clk.common.hw, + [CLK_BUS_I2C9] = &bus_i2c9_clk.common.hw, + [CLK_BUS_I2C10] = &bus_i2c10_clk.common.hw, + [CLK_BUS_I2C11] = &bus_i2c11_clk.common.hw, + [CLK_BUS_I2C12] = &bus_i2c12_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, [CLK_SPIF] = &spif_clk.common.hw, + [CLK_BUS_SPIF] = &bus_spif_clk.common.hw, [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw, [CLK_SPI4] = &spi4_clk.common.hw, + [CLK_BUS_SPI4] = &bus_spi4_clk.common.hw, [CLK_GPADC0_24M] = &gpadc0_24m_clk.common.hw, + [CLK_BUS_GPADC0] = &bus_gpadc0_clk.common.hw, + [CLK_BUS_THS0] = &bus_ths0_clk.common.hw, [CLK_IRRX] = &irrx_clk.common.hw, + [CLK_BUS_IRRX] = &bus_irrx_clk.common.hw, [CLK_IRTX] = &irtx_clk.common.hw, + [CLK_BUS_IRTX] = &bus_irtx_clk.common.hw, + [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw, [CLK_SGPIO] = &sgpio_clk.common.hw, + [CLK_BUS_SGPIO] = &bus_sgpio_clk.common.hw, [CLK_LPC] = &lpc_clk.common.hw, + [CLK_BUS_LPC] = &bus_lpc_clk.common.hw, [CLK_I2SPCM0] = &i2spcm0_clk.common.hw, + [CLK_BUS_I2SPCM0] = &bus_i2spcm0_clk.common.hw, [CLK_I2SPCM1] = &i2spcm1_clk.common.hw, + [CLK_BUS_I2SPCM1] = &bus_i2spcm1_clk.common.hw, [CLK_I2SPCM2] = &i2spcm2_clk.common.hw, [CLK_I2SPCM2_ASRC] = &i2spcm2_asrc_clk.common.hw, + [CLK_BUS_I2SPCM2] = &bus_i2spcm2_clk.common.hw, [CLK_I2SPCM3] = &i2spcm3_clk.common.hw, + [CLK_BUS_I2SPCM3] = &bus_i2spcm3_clk.common.hw, [CLK_I2SPCM4] = &i2spcm4_clk.common.hw, + [CLK_BUS_I2SPCM4] = &bus_i2spcm4_clk.common.hw, [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw, [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, [CLK_DMIC] = &dmic_clk.common.hw, + [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, [CLK_USB01_REF] = &usb01_ref_clk.common.hw, [CLK_USB2_U2_REF] = &usb2_u2_ref_clk.common.hw, [CLK_USB2_SUSPEND] = &usb2_suspend_clk.common.hw, @@ -1677,25 +2160,41 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_SERDES_PHY] = &serdes_phy_clk.common.hw, [CLK_GMAC_PTP] = &gmac_ptp_clk.common.hw, [CLK_GMAC0_PHY] = &gmac0_phy_clk.common.hw, + [CLK_BUS_GMAC0] = &bus_gmac0_clk.common.hw, [CLK_GMAC1_PHY] = &gmac1_phy_clk.common.hw, + [CLK_BUS_GMAC1] = &bus_gmac1_clk.common.hw, [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, + [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, + [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw, [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw, + [CLK_BUS_TCON_LCD2] = &bus_tcon_lcd2_clk.common.hw, [CLK_DSI0] = &dsi0_clk.common.hw, + [CLK_BUS_DSI0] = &bus_dsi0_clk.common.hw, [CLK_DSI1] = &dsi1_clk.common.hw, + [CLK_BUS_DSI1] = &bus_dsi1_clk.common.hw, [CLK_COMBPHY0] = &combphy0_clk.common.hw, [CLK_COMBPHY1] = &combphy1_clk.common.hw, + [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, + [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, [CLK_EDP_TV] = &edp_tv_clk.common.hw, + [CLK_BUS_EDP_TV] = &bus_edp_tv_clk.common.hw, [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw, [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, [CLK_HDMI_TV] = &hdmi_tv_clk.common.hw, + [CLK_BUS_HDMI_TV] = &bus_hdmi_tv_clk.common.hw, [CLK_HDMI_SFR] = &hdmi_sfr_clk.common.hw, [CLK_HDCP_ESM] = &hdcp_esm_clk.common.hw, + [CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw, + [CLK_BUS_DPSS_TOP1] = &bus_dpss_top1_clk.common.hw, [CLK_LEDC] = &ledc_clk.common.hw, + [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw, + [CLK_BUS_DSC] = &bus_dsc_clk.common.hw, [CLK_CSI_MASTER0] = &csi_master0_clk.common.hw, [CLK_CSI_MASTER1] = &csi_master1_clk.common.hw, [CLK_CSI_MASTER2] = &csi_master2_clk.common.hw, [CLK_CSI] = &csi_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, [CLK_ISP] = &isp_clk.common.hw, [CLK_RES_DCAP_24M] = &res_dcap_24m_clk.common.hw, [CLK_APB2JTAG] = &apb2jtag_clk.common.hw, From patchwork Fri Oct 9 15:52:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3583 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id F0AFD1C328B for ; Fri, 9 Oct 2026 18:03:34 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26574-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-26574-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 2583E86233 for ; Fri, 9 Oct 2026 15:55:19 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DD615394794; Fri, 9 Oct 2026 15:54:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="ITLr3OF3" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 563C63546C6 for ; Fri, 9 Oct 2026 15:54:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561285; cv=pass; b=UP6JqNoiWBPZQ1DfXUSlIRAfv61xlALfUQbTaTzKSpqoyXDb1RPiE6nE3ezolR0vEJTMr6hCwDJcmhL5QdsFssoP41zH5jzIab4fMFwYpEV4w6k2NJpHscvW3Osh0sFW6LdIsp5ekozjujBq3XIVyBdvVTX2i/YS2pSTzmsepCM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791561285; c=relaxed/simple; bh=BPEP7VfaUGZbmPcwPq2g9kxvG/EEHrtyDPHj3TSfn7s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kM6J6o0PQSmdIOrJiov9pFUEdzAnFyUPtle31uqgdWo81q35hZ3Bg0oFNA5EFhPT9TRw9adUeEDuMYIEovSxHFXgFP96pDwBsV+2J70T5xLEiSR0WCgLCQRqQHPuSVWpCMs52KLsPd21mD1VI8lb3xuzBopb8mtGsnBzuPk9Idc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=ITLr3OF3; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1791561262; cv=none; d=zohomail.com; s=zohoarc; b=WMSbr0jZA75ZOV4Z4weTVlMsfi4tgIgtw4tndPCn6AG5aPiMRVsYieZMjWc8FXPsv5DJub/p0FCl8CHo+A3L9rrHMBj++p5bl+Jkw+sza96W3ieEi6Oyb4VEqHBy/2YmE1c/b36xf36yxLNHq5u72hDOVW0pmeJlI96wH2vs5rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1791561262; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=es8iG9/s+uOwayLXRDbuv1FAT0r1xEU1YScxX7/b0OE=; b=HhOlqhjXS6+uSMxWp4dc51MDmsxjiIJhhZ7YgAwhMOTYtWREWwCCN3msWH7GuacsyyWdxNbLC5XG5SeMeTpV+GgibWhHh3Z0U7xgPkBHN61NE6Yv0RnvOBrx/bvzk7ptD36KyaMNdJE2Qd5T4bFSJMKOIjpL4XNf2iZxkYubQaA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1791561262; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=es8iG9/s+uOwayLXRDbuv1FAT0r1xEU1YScxX7/b0OE=; b=ITLr3OF3SQcX+hr1ILAoZFZy3+4BZQpLgaX3ro+Ra8vboYJG9+lcQc6W1xcyHY/4 KOH8Sd/JJezTiEhfT2Gp7UgClFDkdmOadwBMxdw/5Q7BsLRr8ZUez+SJeqAddyfCIUE nlDo/jNWRJt7lzkr1KA8ScOORus1RRDhp0c7bVhs= Received: by smtp.zohomail.com with SMTPS id 179156126138686.92257062814383; Fri, 9 Oct 2026 08:54:21 -0700 (PDT) From: Junhui Liu Date: Fri, 09 Oct 2026 23:52:13 +0800 Subject: [PATCH v6 8/8] clk: sunxi-ng: a733: Add reset lines Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261009-a733-clk-v6-8-ae8178fce7e8@pigmoral.tech> References: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> In-Reply-To: <20261009-a733-clk-v6-0-ae8178fce7e8@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Norman Herms , Vinicius Pedrosa X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7059; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=BPEP7VfaUGZbmPcwPq2g9kxvG/EEHrtyDPHj3TSfn7s=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJO8l48t2KPCefdjPtKDcfqW7/oH/4eOX+jVFnpuYPed Qx92rJeHaUsDGJcDLJiiixc/uL/rHV4vh0RaL0PM4eVCWQIAxenAEzEMo6RYfbfRXGbhOtEs17e NtA0fXi/7lbXtZ6fXBVrPh7fftf7x2GGP9wnIsKXJ+w6mTdl15t/ar2Hhf8xhnzXtxS3j9p06dv Sk9wA X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add the reset lines for the Allwinner A733 SoC. These reset control bits are integrated into the Bus Gate Reset (BGR) registers, typically sharing the same register address with their corresponding bus clock gates. Integrate them into the main CCU driver using the existing sunxi-ng ccu_reset framework, allowing the CCU to also function as a reset controller for the SoC. Tested-by: Jerome Brunet Reviewed-by: Andre Przywara Reviewed-by: Chen-Yu Tsai Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 126 +++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c index c26b640fd257..cc2b229e2e6a 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -26,6 +26,7 @@ #include #include "ccu_common.h" +#include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h" @@ -2212,11 +2213,136 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { .num = CLK_FANOUT3 + 1, }; +static const struct ccu_reset_map sun60i_a733_ccu_resets[] = { + [RST_BUS_ITS_PCIE0] = { 0x574, BIT(16) }, + [RST_BUS_IOMMU0_SYS] = { 0x58c, BIT(16) }, + [RST_BUS_MSI_LITE0_AHB] = { 0x594, BIT(16) }, + [RST_BUS_MSI_LITE0_MBUS] = { 0x594, BIT(17) }, + [RST_BUS_MSI_LITE1_AHB] = { 0x59c, BIT(16) }, + [RST_BUS_MSI_LITE1_MBUS] = { 0x59c, BIT(17) }, + [RST_BUS_MSI_LITE2_AHB] = { 0x5a4, BIT(16) }, + [RST_BUS_MSI_LITE2_MBUS] = { 0x5a4, BIT(17) }, + [RST_BUS_IOMMU1_SYS] = { 0x5b4, BIT(16) }, + [RST_BUS_DMA0] = { 0x704, BIT(16) }, + [RST_BUS_DMA1] = { 0x70c, BIT(16) }, + [RST_BUS_SPINLOCK] = { 0x724, BIT(16) }, + [RST_BUS_MSGBOX] = { 0x744, BIT(16) }, + [RST_BUS_PWM0] = { 0x784, BIT(16) }, + [RST_BUS_PWM1] = { 0x78c, BIT(16) }, + [RST_BUS_DBG] = { 0x7a4, BIT(16) }, + [RST_BUS_SYSDAP] = { 0x7ac, BIT(16) }, + [RST_BUS_TIMER0] = { 0x850, BIT(16) }, + [RST_BUS_DE0] = { 0xa04, BIT(16) }, + [RST_BUS_DI] = { 0xa24, BIT(16) }, + [RST_BUS_G2D] = { 0xa44, BIT(16) }, + [RST_BUS_EINK] = { 0xa6c, BIT(16) }, + [RST_BUS_DE_SYS] = { 0xa74, BIT(16) }, + [RST_BUS_VE_ENC0] = { 0xa8c, BIT(16) }, + [RST_BUS_VE_DEC0] = { 0xa8c, BIT(18) }, + [RST_BUS_CE] = { 0xac4, BIT(16) }, + [RST_BUS_CE_SYS] = { 0xac4, BIT(17) }, + [RST_BUS_NPU_CORE] = { 0xb04, BIT(16) }, + [RST_BUS_NPU_AXI] = { 0xb04, BIT(17) }, + [RST_BUS_NPU_AHB] = { 0xb04, BIT(18) }, + [RST_BUS_NPU_SRAM] = { 0xb04, BIT(19) }, + [RST_BUS_GPU0] = { 0xb24, BIT(16) }, + [RST_BUS_DRAM0] = { 0xc0c, BIT(16) }, + [RST_BUS_NAND0] = { 0xc8c, BIT(16) }, + [RST_BUS_MMC0] = { 0xd0c, BIT(16) }, + [RST_BUS_MMC1] = { 0xd1c, BIT(16) }, + [RST_BUS_MMC2] = { 0xd2c, BIT(16) }, + [RST_BUS_MMC3] = { 0xd3c, BIT(16) }, + [RST_BUS_UFS_AHB] = { 0xd8c, BIT(16) }, + [RST_BUS_UFS_AXI] = { 0xd8c, BIT(17) }, + [RST_BUS_UFS_PHY] = { 0xd8c, BIT(18) }, + [RST_BUS_UFS_CORE] = { 0xd8c, BIT(19) }, + [RST_BUS_UART0] = { 0xe00, BIT(16) }, + [RST_BUS_UART1] = { 0xe04, BIT(16) }, + [RST_BUS_UART2] = { 0xe08, BIT(16) }, + [RST_BUS_UART3] = { 0xe0c, BIT(16) }, + [RST_BUS_UART4] = { 0xe10, BIT(16) }, + [RST_BUS_UART5] = { 0xe14, BIT(16) }, + [RST_BUS_UART6] = { 0xe18, BIT(16) }, + [RST_BUS_I2C0] = { 0xe80, BIT(16) }, + [RST_BUS_I2C1] = { 0xe84, BIT(16) }, + [RST_BUS_I2C2] = { 0xe88, BIT(16) }, + [RST_BUS_I2C3] = { 0xe8c, BIT(16) }, + [RST_BUS_I2C4] = { 0xe90, BIT(16) }, + [RST_BUS_I2C5] = { 0xe94, BIT(16) }, + [RST_BUS_I2C6] = { 0xe98, BIT(16) }, + [RST_BUS_I2C7] = { 0xe9c, BIT(16) }, + [RST_BUS_I2C8] = { 0xea0, BIT(16) }, + [RST_BUS_I2C9] = { 0xea4, BIT(16) }, + [RST_BUS_I2C10] = { 0xea8, BIT(16) }, + [RST_BUS_I2C11] = { 0xeac, BIT(16) }, + [RST_BUS_I2C12] = { 0xeb0, BIT(16) }, + [RST_BUS_SPI0] = { 0xf04, BIT(16) }, + [RST_BUS_SPI1] = { 0xf0c, BIT(16) }, + [RST_BUS_SPI2] = { 0xf14, BIT(16) }, + [RST_BUS_SPIF] = { 0xf1c, BIT(16) }, + [RST_BUS_SPI3] = { 0xf24, BIT(16) }, + [RST_BUS_SPI4] = { 0xf2c, BIT(16) }, /* From the vendor kernel. */ + [RST_BUS_GPADC0] = { 0xfc4, BIT(16) }, + [RST_BUS_THS0] = { 0xfe4, BIT(16) }, + [RST_BUS_IRRX] = { 0x1004, BIT(16) }, + [RST_BUS_IRTX] = { 0x100c, BIT(16) }, + [RST_BUS_LRADC] = { 0x1024, BIT(16) }, + [RST_BUS_SGPIO] = { 0x1064, BIT(16) }, /* From the vendor kernel. */ + [RST_BUS_LPC] = { 0x1084, BIT(16) }, /* From the vendor kernel. */ + [RST_BUS_I2SPCM0] = { 0x120c, BIT(16) }, + [RST_BUS_I2SPCM1] = { 0x121c, BIT(16) }, + [RST_BUS_I2SPCM2] = { 0x122c, BIT(16) }, + [RST_BUS_I2SPCM3] = { 0x123c, BIT(16) }, + [RST_BUS_I2SPCM4] = { 0x124c, BIT(16) }, + [RST_BUS_SPDIF] = { 0x128c, BIT(16) }, + [RST_BUS_DMIC] = { 0x12cc, BIT(16) }, + [RST_USB_PHY0] = { 0x1300, BIT(30) }, + [RST_BUS_OHCI0] = { 0x1304, BIT(16) }, + [RST_BUS_EHCI0] = { 0x1304, BIT(20) }, + [RST_BUS_OTG] = { 0x1304, BIT(24) }, + [RST_USB_PHY1] = { 0x1308, BIT(30) }, + [RST_BUS_OHCI1] = { 0x130c, BIT(16) }, + [RST_BUS_EHCI1] = { 0x130c, BIT(20) }, + [RST_BUS_USB2] = { 0x135c, BIT(16) }, + [RST_BUS_PCIE_PWRUP] = { 0x138c, BIT(16) }, + [RST_BUS_PCIE] = { 0x138c, BIT(17) }, + [RST_BUS_SERDES] = { 0x13c4, BIT(16) }, + [RST_BUS_GMAC0] = { 0x141c, BIT(16) }, + [RST_BUS_GMAC0_AXI] = { 0x141c, BIT(17) }, + [RST_BUS_GMAC1] = { 0x142c, BIT(16) }, /* From the vendor kernel. */ + [RST_BUS_GMAC1_AXI] = { 0x142c, BIT(17) }, /* From the vendor kernel. */ + [RST_BUS_TCON_LCD0] = { 0x1504, BIT(16) }, + [RST_BUS_TCON_LCD1] = { 0x150c, BIT(16) }, + [RST_BUS_TCON_LCD2] = { 0x1514, BIT(16) }, /* From the vendor kernel. */ + [RST_BUS_LVDS0] = { 0x1544, BIT(16) }, + [RST_BUS_LVDS1] = { 0x154c, BIT(16) }, + [RST_BUS_DSI0] = { 0x1584, BIT(16) }, + [RST_BUS_DSI1] = { 0x158c, BIT(16) }, + [RST_BUS_TCON_TV0] = { 0x1604, BIT(16) }, + [RST_BUS_TCON_TV1] = { 0x160c, BIT(16) }, + [RST_BUS_EDP] = { 0x164c, BIT(16) }, + [RST_BUS_HDMI_MAIN] = { 0x168c, BIT(16) }, + [RST_BUS_HDMI_SUB] = { 0x168c, BIT(17) }, + [RST_BUS_HDMI_HDCP] = { 0x168c, BIT(18) }, + [RST_BUS_DPSS_TOP0] = { 0x16c4, BIT(16) }, + [RST_BUS_DPSS_TOP1] = { 0x16cc, BIT(16) }, + [RST_BUS_VIDEO_OUT0] = { 0x16e4, BIT(16) }, + [RST_BUS_VIDEO_OUT1] = { 0x16ec, BIT(16) }, + [RST_BUS_LEDC] = { 0x1704, BIT(16) }, + [RST_BUS_DSC] = { 0x1744, BIT(16) }, + [RST_BUS_CSI] = { 0x1844, BIT(16) }, + [RST_BUS_VIDEO_IN] = { 0x1884, BIT(16) }, + [RST_BUS_APB2JTAG] = { 0x1c04, BIT(16) }, +}; + static const struct sunxi_ccu_desc sun60i_a733_ccu_desc = { .ccu_clks = sun60i_a733_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun60i_a733_ccu_clks), .hw_clks = &sun60i_a733_hw_clks, + + .resets = sun60i_a733_ccu_resets, + .num_resets = ARRAY_SIZE(sun60i_a733_ccu_resets), }; static const u32 pll_regs[] = {