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If no such clock is available (for instance because clocks are managed by firmware and not described in DT), the rate is 0 and (0 / 1000000) - 1 underflows to 0xffffffff, which is then written to the register and can break the LPI timers that count in microseconds. Leave the register at its reset value when the CSR clock rate is unknown. The RX watchdog conversion helpers already cope with a missing clock by falling back to clk_ref_rate or returning 0, so nothing else needs to change. This is first hit with the Qualcomm sa8255p ethernet, whose DT has no clocks. Fixes: 68f5d3dc2808 ("net: stmmac: qcom-ethqos: add support for sa8255p") Reported-by: Sashiko Closes: https://lore.kernel.org/all/179052656185.2160803.1751830002645522416@kernel.org/ Signed-off-by: Bartosz Golaszewski --- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index cd6c5d6f42b5445918f277a2b4168d8f473bfca1..259e2ebed8c14dfdb9318da9be03c5f1dc9b1284 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -48,9 +48,14 @@ static void dwmac4_core_init(struct mac_device_info *hw, value = readl(ioaddr + GMAC_CONFIG); writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG); - /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */ + /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1. + * Platforms with firmware-managed clocks may not expose the CSR clock + * to linux, in which case there's no meaningful value to program. + */ clk_rate = clk_get_rate(priv->plat->stmmac_clk); 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ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RCPT_COUNT_GT_50(0.00)[52]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; FREEMAIL_TO(0.00)[kernel.org,lunn.ch,davemloft.net,redhat.com,gmail.com,foss.st.com,st.com,linaro.org,baylibre.com,oss.nxp.com,nxp.com,oss.qualcomm.com,bootlin.com,glider.be,rendec.net]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from] X-Rspamd-Queue-Id: D85861C23A1 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Bartosz Golaszewski Describe the firmware-managed variant of the QCom DesignWare MAC. As the properties here differ a lot from the HLOS-managed variant, lets put it in a separate file. Since we need to update the maximum number of power domains, let's update existing bindings referencing the top-level snps,dwmac.yaml and limit their maxItems for power-domains to 1. Signed-off-by: Bartosz Golaszewski Reviewed-by: Martin Blumenstingl Reviewed-by: Krzysztof Kozlowski Reviewed-by: Lad Prabhakar Reviewed-by: Romain Gantois # For RZ/N1 Signed-off-by: Bartosz Golaszewski --- .../bindings/net/allwinner,sun7i-a20-gmac.yaml | 3 + .../bindings/net/altr,socfpga-stmmac.yaml | 3 + .../bindings/net/amlogic,meson-dwmac.yaml | 3 + .../devicetree/bindings/net/eswin,eic7700-eth.yaml | 3 + .../devicetree/bindings/net/intel,dwmac-plat.yaml | 3 + .../bindings/net/loongson,ls1b-gmac.yaml | 3 + .../bindings/net/loongson,ls1c-emac.yaml | 3 + .../bindings/net/nuvoton,ma35d1-dwmac.yaml | 3 + .../devicetree/bindings/net/nxp,dwmac-imx.yaml | 3 + .../devicetree/bindings/net/nxp,lpc1850-dwmac.yaml | 3 + .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 3 + .../devicetree/bindings/net/qcom,ethqos.yaml | 3 + .../bindings/net/qcom,sa8255p-ethqos.yaml | 107 +++++++++++++++++++++ .../devicetree/bindings/net/renesas,rzn1-gmac.yaml | 3 + .../bindings/net/renesas,rzv2h-gbeth.yaml | 3 + .../devicetree/bindings/net/rockchip-dwmac.yaml | 3 + .../devicetree/bindings/net/snps,dwmac.yaml | 5 +- .../bindings/net/sophgo,cv1800b-dwmac.yaml | 3 + .../bindings/net/sophgo,sg2044-dwmac.yaml | 3 + .../devicetree/bindings/net/spacemit,k3-dwmac.yaml | 3 + .../bindings/net/starfive,jh7110-dwmac.yaml | 3 + .../devicetree/bindings/net/stm32-dwmac.yaml | 3 + .../devicetree/bindings/net/tesla,fsd-ethqos.yaml | 3 + .../devicetree/bindings/net/thead,th1520-gmac.yaml | 3 + .../bindings/net/toshiba,visconti-dwmac.yaml | 3 + MAINTAINERS | 1 + 26 files changed, 181 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml index 23e92be33ac8609a16db530782989caed22a5730..b12632545673b2ad0148a677f45a7447309a43cd 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml @@ -40,6 +40,9 @@ properties: description: PHY regulator + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index d8f90d36d24698e38e4dc7a7c0ce83db7179b876..ce1bd5f2c4702d5ce4c4b669b84406d98a33838a 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -156,6 +156,9 @@ properties: - description: offset of the control register - description: shift within the control register + power-domains: + maxItems: 1 + patternProperties: "^mdio[0-9]$": type: object diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 5c91716d1f21e617543b03c5a90b993f8aee053c..9c9cc3ef384da0270489c21b3426572ea46d9499 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -158,6 +158,9 @@ properties: interrupt-names: const: macirq + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index ba49fd6a086cb92777310bc9e38efe1b3ccd2f7e..b79058b36d704fabb14f2df3c01fe9bfaefdf8a9 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -120,6 +120,9 @@ properties: - description: Optional offset of register controlling TXD delay - description: Optional offset of register controlling RXD delay + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml b/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml index d1522216d32b943993489f2c47dcf97e822b2316..81c123fe6bb9474f537f988814b414e451f88c16 100644 --- a/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml +++ b/Documentation/devicetree/bindings/net/intel,dwmac-plat.yaml @@ -47,6 +47,9 @@ properties: interrupt-names: const: macirq + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml b/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml index c4f3224bad387b87a5b4a3049dabd75f2c4bd42f..c9a131b8d8304c41559a416b324df749c0a87d14 100644 --- a/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml +++ b/Documentation/devicetree/bindings/net/loongson,ls1b-gmac.yaml @@ -66,6 +66,9 @@ properties: - mii - rgmii-id + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml b/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml index 99001b940b8361f69bb917617f857ee99f4b3fa5..49db18423dd807683b9bb297978f5da8ea6cee3d 100644 --- a/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml +++ b/Documentation/devicetree/bindings/net/loongson,ls1c-emac.yaml @@ -65,6 +65,9 @@ properties: - mii - rmii + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml index ab18702e53f9b4800a366febba1a6cf3eba173a4..5301fe64e98b8da843c1c14c7e4b28653b1095fd 100644 --- a/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nuvoton,ma35d1-dwmac.yaml @@ -69,6 +69,9 @@ properties: items: - const: stmmaceth + power-domains: + maxItems: 1 + phy-mode: enum: - rmii diff --git a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml index e5db346beca9649be4f97727b78fda8973095912..b240c76e7dd5254d0c3752610c4aa848a3c3d65b 100644 --- a/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml +++ b/Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml @@ -83,6 +83,9 @@ properties: description: To select RMII reference clock from external. + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml index 05acd9bc7616356e68090ebdd4df20e42f70dd7e..f61188ab0dbe3c0cec5b10f7a65dfaff4dc3898f 100644 --- a/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,lpc1850-dwmac.yaml @@ -51,6 +51,9 @@ properties: items: - const: stmmaceth + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 753a04941659b82b655dad1439ff66f8b37fa18b..fcad2274302d9cff36760184b74918a9835906f7 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -81,6 +81,9 @@ properties: - const: rx - const: ptp_ref + power-domains: + maxItems: 1 + required: - clocks - clock-names diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index 423959cb928d945aa3e758a3c803d12bd61ec42b..ef520f8105773e22c0536ff419dad55fe316e1bd 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -86,6 +86,9 @@ properties: phy-names: const: serdes + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5158481e5e5b0feed5b3dcd2cda2f593b7ff62e4 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,sa8255p-ethqos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ethernet ETHQOS device (firmware managed) + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + - Bartosz Golaszewski + +description: + dwmac based Qualcomm ethernet devices which support Gigabit + ethernet (version v2.3.0 and onwards) with clocks, interconnects, etc. + managed by firmware + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + const: qcom,sa8255p-ethqos + + reg: + maxItems: 2 + + reg-names: + items: + - const: stmmaceth + - const: rgmii + + interrupts: + items: + - description: Combined signal for various interrupt events + - description: The interrupt that occurs when HW safety error triggered + + interrupt-names: + items: + - const: macirq + - const: sfty + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: core + - const: mdio + + phys: + maxItems: 1 + + phy-names: + items: + - const: serdes + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg-names + - power-domains + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet: ethernet@23040000 { + compatible = "qcom,sa8255p-ethqos"; + reg = <0x23040000 0x10000>, + <0x23056000 0x100>; + reg-names = "stmmaceth", "rgmii"; + + iommus = <&apps_smmu 0x120 0x7>; + + interrupts = , + ; + interrupt-names = "macirq", "sfty"; + + dma-coherent; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + phy-handle = <ðernet_phy>; + phy-mode = "2500base-x"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + + power-domains = <&scmi8_pd 0>, <&scmi8_pd 1>; + power-domain-names = "core", "mdio"; + + phys = <&serdes1>; + phy-names = "serdes"; + }; diff --git a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml index 16dd7a2631abf6fb7dc8e0c90755ab1e81915b38..ed0d10a19ca4c47c05f6873c64b0537b90acd15a 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml @@ -44,6 +44,9 @@ properties: phandle pointing to a PCS sub-node compatible with renesas,rzn1-miic.yaml# + power-domains: + maxItems: 1 + required: - compatible diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index c8f76c8e75843e8375ce968d33e125feeb78f999..1c084aafa8f78f4640262ee88c64697a7259c089 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -154,6 +154,9 @@ properties: Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml# (Refer RZ/T2H portion in the DT-binding file) + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml index 80c252845349c4533deff85b052157984d0e2f23..3ec3f6dc2a125908ba98f20b1120311de8967954 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -123,6 +123,9 @@ properties: phy-supply: description: PHY regulator + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 2218a492817fd3d864e0bc529b83fdcbb4ed023b..2c4842404bf675573c7e7200ed674a151af74c4d 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -73,6 +73,7 @@ properties: - nuvoton,ma35d1-dwmac - nxp,s32g2-dwmac - qcom,qcs404-ethqos + - qcom,sa8255p-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos @@ -187,7 +188,8 @@ properties: - enum: [ahb, stmmaceth-ocp] power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 mac-mode: $ref: ethernet-controller.yaml#/properties/phy-connection-type @@ -583,6 +585,7 @@ allOf: - ingenic,x1830-mac - ingenic,x2000-mac - qcom,qcs404-ethqos + - qcom,sa8255p-ethqos - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos diff --git a/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml index b89456f0ef830991135bd17626da98661429596c..e78cbf594c695204040a53ab1e367daa9e12246b 100644 --- a/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/sophgo,cv1800b-dwmac.yaml @@ -49,6 +49,9 @@ properties: reset-names: const: stmmaceth + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml index e8d3814db0e94fdcd0f3ab2a9fa8bab972a97ab5..845e2c67d20037496bb1eec6eb73c99cde74e944 100644 --- a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml @@ -52,6 +52,9 @@ properties: interrupt-names: maxItems: 1 + power-domains: + maxItems: 1 + resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml index 678eccf044f975eb0bed16e7052532e5f19502db..9e0fb995327a925f7c488e5d990563b4f92cd644 100644 --- a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml @@ -56,6 +56,9 @@ properties: reset-names: const: stmmaceth + power-domains: + maxItems: 1 + spacemit,apmu: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml index fdcc61c65f87d1dc15a17b9486cde032ffa7798b..c424e77973921e1f9f18135c3106f1c270c9ac87 100644 --- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml @@ -75,6 +75,9 @@ properties: The argument one is the offset of phy mode selection, the argument two is the shift of phy mode selection. + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 987254900d0da7aab81237f20b1540ad8a17bd21..29b878079ff0c1a0ef95fc63f2035f478ee039b2 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -121,6 +121,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml b/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml index dd7481bb16e59982c26c1a54ae82b8cff85fdfe0..ad635529d676ed6b752ab3bde5152d5cbddcb519 100644 --- a/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml +++ b/Documentation/devicetree/bindings/net/tesla,fsd-ethqos.yaml @@ -67,6 +67,9 @@ properties: - rgmii-rxid - rgmii-txid + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml index b3492a9aa4effa73fadf92a63a76ba8bb65a8769..c859f8bb5d582af8b8782f2f89ab5e6ee3d7a46c 100644 --- a/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml +++ b/Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml @@ -78,6 +78,9 @@ properties: items: - const: macirq + power-domains: + maxItems: 1 + required: - clocks - clock-names diff --git a/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml b/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml index f0f32e18fc8550e6f63b87b60a095972453836c9..efa39eab0256a1102b01872bd848749788c9b4e8 100644 --- a/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml @@ -48,6 +48,9 @@ properties: interrupt-names: const: macirq + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/MAINTAINERS b/MAINTAINERS index 1da3623e77ce1df067a6a5fa6a04c927ee30eb1b..0314b23f003dcf18d60e12eb2b63d34c639862cc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22888,6 +22888,7 @@ L: netdev@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/qcom,ethqos.yaml +F: Documentation/devicetree/bindings/net/qcom,sa8255p-ethqos.yaml F: drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c QUALCOMM FASTRPC DRIVER From patchwork Wed Oct 14 12:36:42 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 3604 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id E19B11C239B for ; Wed, 14 Oct 2026 14:39:44 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=qualcomm.com; dkim=pass header.d=oss.qualcomm.com; spf=pass (sender IP is 172.105.105.114) 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TAGGED_FROM(0.00)[bounces-26633-noreply=patchwork.local]; DKIM_TRACE(0.00)[qualcomm.com:+]; FREEMAIL_TO(0.00)[kernel.org,lunn.ch,davemloft.net,redhat.com,gmail.com,foss.st.com,st.com,linaro.org,baylibre.com,oss.nxp.com,nxp.com,oss.qualcomm.com,bootlin.com,glider.be,rendec.net]; RCVD_TLS_LAST(0.00)[]; DMARC_POLICY_ALLOW(0.00)[qualcomm.com,reject]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: E19B11C239B X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Call phy_set_mode_ext() before phy_power_on() in qcom_ethqos_serdes_powerup(). This is harmless for existing users but on SCMI systems this is required for the PHY driver to select the right performance level - which translates to the link speed. This is done ahead of adding support for the firmware-managed EMAC on Qualcomm sa8255p. Signed-off-by: Bartosz Golaszewski Tested-by: Mohd Ayaan Anwar Reviewed-by: Mohd Ayaan Anwar --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index ac7d6d3e205a1ab5b391def879d6f1033a0961b6..e2e611a4d2c06bd567e9d5e353b3a4893623de6c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -601,10 +601,22 @@ static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) if (ret) return ret; + if (ethqos->phy_mode == PHY_INTERFACE_MODE_SGMII || + ethqos->phy_mode == PHY_INTERFACE_MODE_2500BASEX) { + ret = phy_set_mode_ext(ethqos->serdes_phy, PHY_MODE_ETHERNET, + ethqos->phy_mode); + if (ret) + goto err_out; + } + ret = phy_power_on(ethqos->serdes_phy); if (ret) - phy_exit(ethqos->serdes_phy); + goto err_out; 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It is set once at probe from the DT phy-mode property and never updated. phylink resolves the actual runtime interface and passes it to the mac_finish() callback. On platforms that only ever operate at one speed these two values are always the same, but when the interface changes at runtime - for example switching between SGMII and 2500BASE-X - the stored value becomes stale. The next serdes_powerup() call, on a subsequent link cycle, then reinitializes the SerDes to the wrong mode. Update ethqos->phy_mode from the interface argument in ethqos_mac_finish_serdes() so that it always reflects the last resolved interface. With that, we now update the phy_mode to the runtime-resolved interface, so any subsequent resume with a 1G SGMII link skips the loopback setup and the DMA reset hangs. To remedy this, extend the guard to include PHY_INTERFACE_MODE_SGMII. Signed-off-by: Bartosz Golaszewski Reviewed-by: Mohd Ayaan Anwar --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index e2e611a4d2c06bd567e9d5e353b3a4893623de6c..f7cc46d86591a220a183529a8f89456f9153385d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -190,7 +190,8 @@ static void qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable) { if (!ethqos->needs_sgmii_loopback || - ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX) + (ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX && + ethqos->phy_mode != PHY_INTERFACE_MODE_SGMII)) return; rgmii_updatel(ethqos, @@ -637,6 +638,12 @@ static int ethqos_mac_finish_serdes(struct net_device *ndev, void *priv, qcom_ethqos_set_sgmii_loopback(ethqos, false); + /* The interface mode is only known once phylink has resolved it and + * may change at runtime, so keep it in sync for later + * serdes_powerup() and qcom_ethqos_set_sgmii_loopback() calls. + */ + ethqos->phy_mode = interface; + if (interface == PHY_INTERFACE_MODE_SGMII || interface == PHY_INTERFACE_MODE_2500BASEX) ret = phy_set_mode_ext(ethqos->serdes_phy, PHY_MODE_ETHERNET, From patchwork Wed Oct 14 12:36:44 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 3603 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id CAD6F1C239B for ; Wed, 14 Oct 2026 14:39:29 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=qualcomm.com; dkim=pass header.d=oss.qualcomm.com; spf=pass (sender IP is 172.232.135.74) smtp.mailfrom=linux-sunxi+bounces-26635-noreply=patchwork.local@lists.linux.dev smtp.helo=sto.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.232.135.74 as permitted sender) client-ip=172.232.135.74; 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Wed, 14 Oct 2026 05:37:22 -0700 (PDT) X-Received: by 2002:a05:620a:a0d2:20b0:93e:c12c:fbc3 with SMTP id af79cd13be357-93ec12d08b4mr1718223885a.80.1791981441505; Wed, 14 Oct 2026 05:37:21 -0700 (PDT) Received: from brgl-qcom.local ([2a01:cb1d:dc:7e00:8916:7b9b:97a2:6c96]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a19f318c31sm206122615e9.3.2026.10.14.05.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 05:37:20 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 14 Oct 2026 14:36:44 +0200 Subject: [PATCH net-next v16 5/7] net: stmmac: qcom-ethqos: reuse the address of ethqos_emac_driver_data Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20261014-qcom-sa8255p-emac-v16-5-0266c2ead980@oss.qualcomm.com> References: <20261014-qcom-sa8255p-emac-v16-0-0266c2ead980@oss.qualcomm.com> In-Reply-To: <20261014-qcom-sa8255p-emac-v16-0-0266c2ead980@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Vinod Koul , Giuseppe Cavallaro , Chen-Yu Tsai , Jernej Skrabec , Neil Armstrong , Kevin Hilman , Jerome Brunet , Shawn Guo , Fabio Estevam , Jan Petrous , s32@nxp.com, Mohd Ayaan Anwar , Romain Gantois , Geert Uytterhoeven , Magnus Damm , Maxime Ripard , Christophe Roullier , Bartosz Golaszewski , Eric Dumazet , Radu Rendec Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Drew Fustini , linux-sunxi@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, brgl@kernel.org, Bartosz Golaszewski , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5580; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=NZAxb9MK43O2wa2aiDj23ZEiKR9RAVihBgD6wcTqioI=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBqz3dq0Zvsjdv0r+UH1RTZk+xo3PmAYIDeAPN2E TDZo6tkzHOJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCas93agAKCRAFnS7L/zaE w4IyD/9DJPXkhz5MqqgMDev686ljyN6tBlY8ZWbnZuVhfixY62045lCO1EZ3f5jvhFWv6O1/wtC wvRP1Grbg9Jy9VS2elo3KN2kTRlldUnvIXU+nGDWE+FT39yTXp08BUXPVH2Iqcn7spnoIubr8rJ m6WN815GME9Z1m6OTuGFhBScp2oE79onUyuVtXcXp4Yrbm61wEVt6M+XV8LBmIwS71xOvkG+xjV Ok7Hl3ceVOft9xjqH4aP3mYHSHIDwhk35CYLsP1PhK0zsBWya6s9+CJBIrhPU0cA73aYSf6G2Na m7SxrQyY/kTjnd51aa4uOiYRxjgELXdtuqO51++CcGODiyVUJWeLCVkVCCoW2ZxhO01yUZMGgDl XNHuL8WQKOm089W9rFbE/P+zomV7KsnKVGaBuWE4EbmE7VoG9Xk2uk721EIK6V4GncGeFpDe8Pm AVaX+itiLOoWIl0JmcTZAaHES3cxogTpHa5CgJdKg+4ZoolwSr4EEGkQu7wsYmmFC0EPyoxdCCQ qflgS/tw+2p9C3/2BY1TKlfodcFroOGtgfvEvpzlvbSeK3keUmnntRKU3F1TX5QtSDhvS5IgzXc swJpVWtUA72bb/dUu81L7pxkqNi5tHxL6HgO46f7ap40p/+CpSHCbzScNeSNwFUQvWCQMb/bE4k ZdcW1bOynzELXyA== X-Developer-Key: i=bartosz.golaszewski@oss.qualcomm.com; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDA1MCBTYWx0ZWRfXz8s0Y6WWcBBR VfYj1FRAEUIfllJLqfrAiI9BcQC8/xVWxnWNNYRM2d6a639mmxwbrwX3NuMQU1e4Nb6dJMizKqq wrA7/pH1RNlrR5oGDwz9puJLckkstELUyNqIPDGn50zNbf3D9GkJ+zIhAN/JPoUBeaz7JWIrUQ7 KAIwEl7PXgZM/oC9MQFqWF8PYNYdcuaHc0mX4DxRJcEaKRp2uSProOilEfUHJdjqUKOTCrHkRqu WjNMFymXe79Dkm0y6uoTlHhuNJ3SuX5BYPiuk+L6CFZ1EOqfnhPHUUiXINzVrJ3BKo/9udxisq6 2XsbuYFu/V6FIu2iEa+QNXbDbZeWpTRZVKiM6AY94jcuTUAzKgP6y/tXIwbUHnN8iYYuqXs6vzj l4MZOg90DcfSzIhm2MopwPuLQWWsujEMcM8UP6ysT/IVEvStZRpmVgVkwVT18fcxWYS9LtXyDxQ h2EqaT71LkwRB+o/Xog== X-Authority-Analysis: v=2.4 cv=LPPz05W9 c=1 sm=1 tr=0 ts=6acf7783 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=fhsz3KazkzAS9s_vSxIA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDA1MCBTYWx0ZWRfX+p/5q1D5r06N hhoWhutSh5snsN6aK5b9JHl8yKKFwrxRQ9bSQ0bHH38K3SJPAV+pvOON2GaxFeflEAxpJUZHdOk O7ytcRD6S624Ql0C1/+KMCS+ocqDmwg= X-Proofpoint-ORIG-GUID: Z-lGT25AQ0aySXIOkLcuYBNS88dgoTq_ X-Proofpoint-GUID: Z-lGT25AQ0aySXIOkLcuYBNS88dgoTq_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140050 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Instead of needlessly copying the fields of ethqos_emac_driver_data into struct qcom_ethqos, just use the address of the former as a reference. It's .rodata after all. This is done in order to avoid having either two calls to of_device_get_match_data() or having to extend the latter with another field when adding support for SCMI. Signed-off-by: Bartosz Golaszewski Tested-by: Mohd Ayaan Anwar Reviewed-by: Mohd Ayaan Anwar --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 37 ++++++++-------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index f7cc46d86591a220a183529a8f89456f9153385d..f840ba4c02df616410759f49af8dc8fa0635987d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -103,12 +103,7 @@ struct qcom_ethqos { struct clk *link_clk; struct phy *serdes_phy; phy_interface_t phy_mode; - - const struct ethqos_emac_por *rgmii_por; - unsigned int num_rgmii_por; - bool rgmii_config_loopback_en; - bool has_emac_ge_3; - bool needs_sgmii_loopback; + const struct ethqos_emac_driver_data *data; }; static u32 rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) @@ -189,7 +184,7 @@ static int ethqos_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, static void qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable) { - if (!ethqos->needs_sgmii_loopback || + if (!ethqos->data->needs_sgmii_loopback || (ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX && ethqos->phy_mode != PHY_INTERFACE_MODE_SGMII)) return; @@ -323,7 +318,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) /* Set DLL_EN */ rgmii_setmask(ethqos, SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG); - if (!ethqos->has_emac_ge_3) { + if (!ethqos->data->has_emac_ge_3) { rgmii_clrmask(ethqos, SDCC_DLL_MCLK_GATING_EN, SDCC_HC_REG_DLL_CONFIG); @@ -353,7 +348,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2); - if (!ethqos->has_emac_ge_3) { + if (!ethqos->data->has_emac_ge_3) { rgmii_clrmask(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS, SDCC_HC_REG_DLL_CONFIG2); @@ -433,7 +428,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, RGMII_IO_MACRO_CONFIG2); - if (speed == SPEED_1000 || ethqos->has_emac_ge_3) + if (speed == SPEED_1000 || ethqos->data->has_emac_ge_3) rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, RGMII_IO_MACRO_CONFIG2); else @@ -457,7 +452,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) * in practice this becomes PRG_RCLK_DLY = 52 * 4 / * (2 * RX delay ns) */ - if (ethqos->has_emac_ge_3) { + if (ethqos->data->has_emac_ge_3) { /* 0.9 ns */ prg_rclk_dly = 115; } else { @@ -473,7 +468,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) SDCC_HC_REG_DDR_CONFIG); } - if (ethqos->rgmii_config_loopback_en) + if (ethqos->data->rgmii_config_loopback_en) loopback = RGMII_CONFIG_LOOPBACK_EN; else loopback = 0; @@ -496,9 +491,9 @@ static void ethqos_fix_mac_speed_rgmii(void *bsp_priv, dev = ðqos->pdev->dev; /* Reset to POR values and enable clk */ - for (i = 0; i < ethqos->num_rgmii_por; i++) - rgmii_writel(ethqos, ethqos->rgmii_por[i].value, - ethqos->rgmii_por[i].offset); + for (i = 0; i < ethqos->data->num_rgmii_por; i++) + rgmii_writel(ethqos, ethqos->data->rgmii_por[i].value, + ethqos->data->rgmii_por[i].offset); ethqos_set_func_clk_en(ethqos); @@ -512,7 +507,7 @@ static void ethqos_fix_mac_speed_rgmii(void *bsp_priv, rgmii_setmask(ethqos, SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG); - if (ethqos->has_emac_ge_3) { + if (ethqos->data->has_emac_ge_3) { if (speed == SPEED_1000) { rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL); rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL); @@ -539,7 +534,7 @@ static void ethqos_fix_mac_speed_rgmii(void *bsp_priv, SDCC_HC_REG_DLL_CONFIG); /* Set USR_CTL bit 26 with mask of 3 bits */ - if (!ethqos->has_emac_ge_3) + if (!ethqos->data->has_emac_ge_3) rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL); @@ -753,11 +748,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) "Failed to map rgmii resource\n"); data = of_device_get_match_data(dev); - ethqos->rgmii_por = data->rgmii_por; - ethqos->num_rgmii_por = data->num_rgmii_por; - ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en; - ethqos->has_emac_ge_3 = data->has_emac_ge_3; - ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback; + ethqos->data = data; ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); if (IS_ERR(ethqos->link_clk)) @@ -794,7 +785,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) plat_dat->dump_debug_regs = rgmii_dump; plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; 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ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; DMARC_POLICY_ALLOW(0.00)[qualcomm.com,reject]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; FREEMAIL_TO(0.00)[kernel.org,lunn.ch,davemloft.net,redhat.com,gmail.com,foss.st.com,st.com,linaro.org,baylibre.com,oss.nxp.com,nxp.com,oss.qualcomm.com,bootlin.com,glider.be,rendec.net]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from] X-Rspamd-Queue-Id: 9F8311C239B X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Ahead of adding support for firmware-controlled EMAC variants, extend the ethqos_emac_driver_data structure with a setup() callback, implement it for the existing models and move all operations not required in SCMI mode into it. Signed-off-by: Bartosz Golaszewski Tested-by: Mohd Ayaan Anwar Reviewed-by: Mohd Ayaan Anwar --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 94 ++++++++++++++++------ 1 file changed, 68 insertions(+), 26 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index f840ba4c02df616410759f49af8dc8fa0635987d..4e9c534fb240f0e08695282bb66cf6134415cc71 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -81,6 +82,8 @@ #define SGMII_10M_RX_CLK_DVDR 0x31 +struct qcom_ethqos; + struct ethqos_emac_por { unsigned int offset; unsigned int value; @@ -95,6 +98,8 @@ struct ethqos_emac_driver_data { const char *link_clk_name; struct dwmac4_addrs dwmac4_addrs; bool needs_sgmii_loopback; + int (*setup)(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat); }; struct qcom_ethqos { @@ -200,6 +205,9 @@ static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); } +static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat); + static const struct ethqos_emac_por emac_v2_3_0_por[] = { { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, @@ -214,6 +222,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = { .num_rgmii_por = ARRAY_SIZE(emac_v2_3_0_por), .rgmii_config_loopback_en = true, .has_emac_ge_3 = false, + .setup = ethqos_hlos_setup, }; static const struct ethqos_emac_por emac_v2_1_0_por[] = { @@ -230,6 +239,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0_data = { .num_rgmii_por = ARRAY_SIZE(emac_v2_1_0_por), .rgmii_config_loopback_en = false, .has_emac_ge_3 = false, + .setup = ethqos_hlos_setup, }; static const struct ethqos_emac_por emac_v3_0_0_por[] = { @@ -262,6 +272,7 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = { .mtl_low_cred = 0x00008024, .mtl_low_cred_offset = 0x1000, }, + .setup = ethqos_hlos_setup, }; static const struct ethqos_emac_por emac_v4_0_0_por[] = { @@ -297,6 +308,7 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { .mtl_low_cred = 0x00008024, .mtl_low_cred_offset = 0x1000, }, + .setup = ethqos_hlos_setup, }; static int ethqos_dll_configure(struct qcom_ethqos *ethqos) @@ -695,6 +707,58 @@ static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate); } +static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat) +{ + struct platform_device *pdev = ethqos->pdev; + struct device *dev = &pdev->dev; + int ret; + + ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); + if (IS_ERR(ethqos->rgmii_base)) + return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), + "Failed to map rgmii resource\n"); + + ethqos->link_clk = devm_clk_get(dev, ethqos->data->link_clk_name ?: "rgmii"); + if (IS_ERR(ethqos->link_clk)) + return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), + "Failed to get link_clk\n"); + + plat_dat->clks_config = ethqos_clks_config; + + ret = ethqos_clks_config(ethqos, true); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + if (ret) + return ret; + + ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface, SPEED_1000); + qcom_ethqos_set_sgmii_loopback(ethqos, true); + ethqos_set_func_clk_en(ethqos); + + switch (ethqos->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_rgmii; + break; + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; + break; + default: + break; + } + + plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate; + plat_dat->dump_debug_regs = rgmii_dump; + + return 0; +} + static int qcom_ethqos_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -716,23 +780,20 @@ static int qcom_ethqos_probe(struct platform_device *pdev) "dt configuration failed\n"); } - plat_dat->clks_config = ethqos_clks_config; - ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); if (!ethqos) return -ENOMEM; ethqos->phy_mode = plat_dat->phy_interface; + switch (ethqos->phy_mode) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: - plat_dat->fix_mac_speed = ethqos_fix_mac_speed_rgmii; break; case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_SGMII: - plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; plat_dat->mac_finish = ethqos_mac_finish_serdes; break; default: @@ -742,24 +803,13 @@ static int qcom_ethqos_probe(struct platform_device *pdev) } ethqos->pdev = pdev; - ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); - if (IS_ERR(ethqos->rgmii_base)) - return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), - "Failed to map rgmii resource\n"); - data = of_device_get_match_data(dev); ethqos->data = data; - ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); - if (IS_ERR(ethqos->link_clk)) - return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), - "Failed to get link_clk\n"); - - ret = ethqos_clks_config(ethqos, true); - if (ret) - return ret; + if (WARN_ON(!data->setup)) + return -EINVAL; - ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + ret = data->setup(ethqos, plat_dat); if (ret) return ret; @@ -768,12 +818,6 @@ static int qcom_ethqos_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy), "Failed to get serdes phy\n"); - ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface, - SPEED_1000); - - qcom_ethqos_set_sgmii_loopback(ethqos, true); - ethqos_set_func_clk_en(ethqos); - /* The clocks are controlled by firmware, so we don't know for certain * what clock rate is being used. Hardware documentation mentions that * the AHB slave clock will be in the range of 50 to 100MHz, which @@ -781,8 +825,6 @@ static int qcom_ethqos_probe(struct platform_device *pdev) */ plat_dat->clk_csr = STMMAC_CSR_60_100M; plat_dat->bsp_priv = ethqos; - plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate; - plat_dat->dump_debug_regs = rgmii_dump; plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; plat_dat->core_type = DWMAC_CORE_GMAC4; if (data->has_emac_ge_3) From patchwork Wed Oct 14 12:36:46 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 3606 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 897991C239B for ; Wed, 14 Oct 2026 14:40:26 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=qualcomm.com; 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Unlike the previously supported variants, this one's power management is done in the firmware over SCMI. This is modeled in linux using power domains so add a new emac data variant and a separate setup callback. Signed-off-by: Bartosz Golaszewski --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 111 +++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 4e9c534fb240f0e08695282bb66cf6134415cc71..d59be76a20916de3febed400a64aff9763aac45d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -98,6 +98,11 @@ struct ethqos_emac_driver_data { const char *link_clk_name; struct dwmac4_addrs dwmac4_addrs; bool needs_sgmii_loopback; + /* Fixed PTP reference clock rate, used on SCMI platforms where + * firmware does not implement the clock protocol allowing linux to + * query it. + */ + unsigned long ptp_clk_rate; int (*setup)(struct qcom_ethqos *ethqos, struct plat_stmmacenet_data *plat_dat); }; @@ -108,6 +113,7 @@ struct qcom_ethqos { struct clk *link_clk; struct phy *serdes_phy; phy_interface_t phy_mode; + struct dev_pm_domain_list *pds; const struct ethqos_emac_driver_data *data; }; @@ -207,6 +213,8 @@ static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, struct plat_stmmacenet_data *plat_dat); +static int ethqos_scmi_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat); static const struct ethqos_emac_por emac_v2_3_0_por[] = { { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, @@ -311,6 +319,30 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { .setup = ethqos_hlos_setup, }; +static const struct ethqos_emac_driver_data emac_v4_0_0_scmi_data = { + .has_emac_ge_3 = true, + .needs_sgmii_loopback = true, + .dma_addr_width = 36, + .ptp_clk_rate = 230400000, + .dwmac4_addrs = { + .dma_chan = 0x00008100, + .dma_chan_offset = 0x1000, + .mtl_chan = 0x00008000, + .mtl_chan_offset = 0x1000, + .mtl_ets_ctrl = 0x00008010, + .mtl_ets_ctrl_offset = 0x1000, + .mtl_txq_weight = 0x00008018, + .mtl_txq_weight_offset = 0x1000, + .mtl_send_slp_cred = 0x0000801c, + .mtl_send_slp_cred_offset = 0x1000, + .mtl_high_cred = 0x00008020, + .mtl_high_cred_offset = 0x1000, + .mtl_low_cred = 0x00008024, + .mtl_low_cred_offset = 0x1000, + }, + .setup = ethqos_scmi_setup, +}; + static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { struct device *dev = ðqos->pdev->dev; @@ -759,6 +791,84 @@ static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, return 0; } +static const char *const ethqos_scmi_pd_names[] = { "core", "mdio" }; + +static int ethqos_scmi_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat) +{ + const struct dev_pm_domain_attach_data pd_data = { + .pd_names = ethqos_scmi_pd_names, + .num_pd_names = ARRAY_SIZE(ethqos_scmi_pd_names), + .pd_flags = PD_FLAG_DEV_LINK_ON, + }; + + struct platform_device *pdev = ethqos->pdev; + struct device *dev = &pdev->dev; + int ret; + + ret = devm_pm_domain_attach_list(dev, &pd_data, ðqos->pds); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to attach power domains\n"); + + /* + * The MAC AXI/AHB clocks are owned by firmware and brought up through + * the "core" and "mdio" SCMI power domains above, while the SerDes + * lane is powered by the SerDes PHY's own power domain from + * serdes_powerup() in stmmac_open(). The MAC wrapper itself, however + * is in the kernel's register space: the wrapper bit that loops the + * PHY TX clock into the MAC's clk_rx_i - needed because no recovered + * RX clock exists yet - is not configured by firmware. Without it, + * clk_rx_i never toggles and the DMA SW-reset polled in + * dwmac4_dma_reset() never completes. + * + * Map the wrapper and program the same loopback/functional clock bits + * the non-firmware platforms rely on (see ethqos_clks_config) so the + * RX clock is present by the time the DMA engine is reset. + */ + ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); + if (IS_ERR(ethqos->rgmii_base)) + return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), + "Failed to map rgmii resource\n"); + + /* + * Register clks_config to run on every subsequent runtime resume, + * which stmmac performs after the power domains are on but before + * serdes_powerup() and the DMA reset. This alone isn't enough for + * the very first reset done from stmmac_open(), though: probe() + * fakes the device into RPM_ACTIVE without invoking the resume + * callback, so whether clks_config() has run by then depends on + * whether the device has already gone through one real suspend/resume + * cycle in the meantime. Call it here explicitly so the wrapper is + * always configured before the first DMA reset regardless of that + * timing. + */ + plat_dat->clks_config = ethqos_clks_config; + + ret = ethqos_clks_config(ethqos, true); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + if (ret) + return ret; + + plat_dat->clk_ptp_rate = ethqos->data->ptp_clk_rate; + + switch (ethqos->phy_mode) { + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; + break; + default: + /* The firmware-managed SerDes only supports SGMII modes. */ + return dev_err_probe(dev, -EINVAL, "Unsupported phy-mode: %s\n", + phy_modes(ethqos->phy_mode)); + } + + return 0; +} + static int qcom_ethqos_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -851,6 +961,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) static const struct of_device_id qcom_ethqos_match[] = { { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, + { .compatible = "qcom,sa8255p-ethqos", .data = &emac_v4_0_0_scmi_data}, { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},