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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-850f8458d8esm565721a34.1.2026.10.23.14.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 14:19:31 -0700 (PDT) From: James Hilliard Date: Fri, 23 Oct 2026 15:19:27 -0600 Subject: [PATCH v2 1/3] dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Message-Id: <20261023-submit-h616-uart-fifo-v1-v2-1-af0593504635@gmail.com> References: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> In-Reply-To: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4?= =?utf-8?q?rvinen?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.19 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.18)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:helo,sea.lore.kernel.org:rdns]; FORGED_SENDER_MAILLIST(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; RCPT_COUNT_TWELVE(0.00)[16]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,gmail.com]; TAGGED_RCPT(0.00)[dt]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; MID_RHS_MATCH_FROM(0.00)[]; TO_DN_SOME(0.00)[]; FREEMAIL_FROM(0.00)[gmail.com]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.77.114.92:received,174.29.1.49:received,209.85.210.46:received]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; TAGGED_FROM(0.00)[bounces-26832-noreply=patchwork.local]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc20261015:i=2]; FREEMAIL_TO(0.00)[linuxfoundation.org,kernel.org,linux.intel.com,gmail.com,sholland.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 1D7EB1C0982 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner H616 UART has 256-byte FIFOs but does not implement the DesignWare component parameter register used to discover their size. Add a compatible to identify this integration and its fixed FIFO configuration. Retain snps,dw-apb-uart as a fallback. Signed-off-by: James Hilliard --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index e2ca126d58ba..fc1289073241 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -60,6 +60,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - allwinner,sun50i-h616-uart - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart From patchwork Fri Oct 23 21:19:28 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hilliard X-Patchwork-Id: 3710 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 519891C0982 for ; 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-850f8458d8esm565721a34.1.2026.10.23.14.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 14:19:33 -0700 (PDT) From: James Hilliard Date: Fri, 23 Oct 2026 15:19:28 -0600 Subject: [PATCH v2 2/3] serial: 8250_dw: configure the Allwinner H616 UART X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Message-Id: <20261023-submit-h616-uart-fifo-v1-v2-2-af0593504635@gmail.com> References: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> In-Reply-To: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4?= =?utf-8?q?rvinen?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.19 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.18)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:helo,sea.lore.kernel.org:rdns]; FORGED_SENDER_MAILLIST(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; RCPT_COUNT_TWELVE(0.00)[16]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,gmail.com]; TAGGED_RCPT(0.00)[dt]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; MID_RHS_MATCH_FROM(0.00)[]; TO_DN_SOME(0.00)[]; FREEMAIL_FROM(0.00)[gmail.com]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.77.114.92:received,174.29.1.49:received,209.85.210.42:received]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; TAGGED_FROM(0.00)[bounces-26833-noreply=patchwork.local]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc20261015:i=2]; FREEMAIL_TO(0.00)[linuxfoundation.org,kernel.org,linux.intel.com,gmail.com,sholland.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 519891C0982 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= H616 has 256-byte transmit and receive FIFOs, but its optional DesignWare component parameter register reads as zero. Generic 16550 probing leaves the port using the 16-byte FIFO configuration and its trigger-level table. DMA attachment also depends on a FIFO size being available during probe, so these ports do not reach the existing 8250 DMA path. Keep PORT_16550A and supply the FIFO size, transmit load and capabilities when matching the H616 platform data. Provide receive-trigger callbacks for the documented thresholds of 1, 64, 128 and 254 bytes. The normal 16550A half-full trigger selects 128 bytes on this integration. Serialize trigger changes with termios and hold a runtime PM reference while programming FCR, preserving the FIFO contents. Advertise automatic flow control so CRTSCTS enables MCR.AFCE. The DesignWare termios path selects hardware CTS handling, so the capability must be present for the corresponding hardware control to be enabled. Skip optional-register probing for this fixed configuration. H616 has debug-divisor and RS485 control registers at the offsets used to detect DesignWare hardware RS485 and fractional-divisor support. Probing these offsets writes unrelated registers and can select incompatible callbacks. Keep the BUSY-safe integer divisor hook and software RS485 handling. Use the existing SKIP_SET_RATE quirk to keep the UART clock enabled during termios changes. Its clock is a gate on the shared APB2 source, rather than an independent baud-rate generator. Attach DMA from the fixed configuration before registering the port. Configure single-byte RX and TX bursts because the peripheral request can correspond to just one character. The existing startup path requests the firmware-described channels and falls back to PIO when they are unavailable or the port is a kernel console. Signed-off-by: James Hilliard --- drivers/tty/serial/8250/8250_dw.c | 87 +++++++++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 8 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index eca02e8bd6d1..b9f5cb61f2b6 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,11 @@ struct dw8250_platform_data { unsigned int quirks; }; +static const struct dw8250_platform_data dw8250_h616_data = { + .usr_reg = DW_UART_USR, + .quirks = DW_UART_QUIRK_SKIP_SET_RATE, +}; + struct dw8250_data { struct dw8250_port_data data; const struct dw8250_platform_data *pdata; @@ -630,6 +636,66 @@ static void dw8250_shutdown(struct uart_port *port) d->no_int_count = 0; } +static const u8 dw8250_h616_rxtrig_bytes[] = { 1, 64, 128, 254 }; + +static int dw8250_h616_get_rxtrig(struct uart_port *p) +{ + struct uart_8250_port *up = up_to_u8250p(p); + + guard(uart_port_lock_irqsave)(p); + + return dw8250_h616_rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; +} + +static int dw8250_h616_set_rxtrig(struct uart_port *p, unsigned char bytes) +{ + struct uart_8250_port *up = up_to_u8250p(p); + int i, ret; + + /* Use the nearest lower threshold, as the generic 8250 implementation does. */ + for (i = 1; i < ARRAY_SIZE(dw8250_h616_rxtrig_bytes); i++) + if (bytes < dw8250_h616_rxtrig_bytes[i]) + break; + + guard(mutex)(&p->state->port.mutex); + + ret = pm_runtime_resume_and_get(p->dev); + if (ret < 0) + return ret; + + scoped_guard(uart_port_lock_irqsave, p) { + up->fcr &= ~UART_FCR_TRIGGER_MASK; + up->fcr |= (i - 1) << UART_FCR_R_TRIG_SHIFT; + /* Changing the trigger alone preserves the FIFO contents. */ + serial_port_out(p, UART_FCR, up->fcr); + } + pm_runtime_put(p->dev); + + return 0; +} + +static void dw8250_h616_setup(struct uart_8250_port *up, struct dw8250_data *data) +{ + struct uart_port *p = &up->port; + + p->type = PORT_16550A; + p->flags |= UPF_FIXED_TYPE; + p->fifosize = 256; + up->tx_loadsz = 256; + up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT | UART_CAP_AFE; + p->get_rxtrig = dw8250_h616_get_rxtrig; + p->set_rxtrig = dw8250_h616_set_rxtrig; + p->rs485_config = serial8250_em485_config; + p->rs485_supported = serial8250_em485_supported; + up->rs485_start_tx = serial8250_em485_start_tx; + up->rs485_stop_tx = serial8250_em485_stop_tx; + + /* A peripheral request can correspond to just one character. */ + data->data.dma.rxconf.src_maxburst = 1; + data->data.dma.txconf.dst_maxburst = 1; + up->dma = &data->data.dma; +} + static int dw8250_probe(struct platform_device *pdev) { struct uart_8250_port uart = {}, *up = &uart; @@ -765,14 +831,18 @@ static int dw8250_probe(struct platform_device *pdev) dw8250_setup_dma_filter(p, data); - if (!data->skip_autocfg) - dw8250_setup_port(p); - - /* If we have a valid fifosize, try hooking up DMA */ - if (p->fifosize) { - data->data.dma.rxconf.src_maxburst = p->fifosize / 4; - data->data.dma.txconf.dst_maxburst = p->fifosize / 4; - up->dma = &data->data.dma; + if (data->pdata == &dw8250_h616_data) { + dw8250_h616_setup(up, data); + } else { + if (!data->skip_autocfg) + dw8250_setup_port(p); + + /* If we have a valid fifosize, try hooking up DMA */ + if (p->fifosize) { + data->data.dma.rxconf.src_maxburst = p->fifosize / 4; + data->data.dma.txconf.dst_maxburst = p->fifosize / 4; + up->dma = &data->data.dma; + } } data->data.uport = serial8250_register_8250_port(up); @@ -904,6 +974,7 @@ static const struct dw8250_platform_data dw8250_tda54 = { static const struct of_device_id dw8250_of_match[] = { { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, + { .compatible = "allwinner,sun50i-h616-uart", .data = &dw8250_h616_data }, { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, From patchwork Fri Oct 23 21:19:29 2026 Content-Type: text/plain; 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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-850f8458d8esm565721a34.1.2026.10.23.14.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 14:19:34 -0700 (PDT) From: James Hilliard Date: Fri, 23 Oct 2026 15:19:29 -0600 Subject: [PATCH v2 3/3] arm64: dts: allwinner: h616: identify the UART integration X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Message-Id: <20261023-submit-h616-uart-fifo-v1-v2-3-af0593504635@gmail.com> References: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> In-Reply-To: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4?= =?utf-8?q?rvinen?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.19 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.18)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FROM_HAS_DN(0.00)[]; TAGGED_RCPT(0.00)[dt]; DBL_PROHIBIT(0.00)[0.76.76.208:email,0.76.80.184:email,0.76.78.96:email,0.61.94.240:email,0.76.79.40:email,0.76.75.64:email]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:helo,sea.lore.kernel.org:rdns]; RCPT_COUNT_TWELVE(0.00)[16]; FORGED_SENDER_MAILLIST(0.00)[]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,gmail.com]; RCVD_COUNT_FIVE(0.00)[6]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; TAGGED_FROM(0.00)[bounces-26834-noreply=patchwork.local]; FREEMAIL_FROM(0.00)[gmail.com]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; TO_DN_SOME(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; FREEMAIL_TO(0.00)[linuxfoundation.org,kernel.org,linux.intel.com,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc20261015:i=2]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 2334D1C0B4C X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Use the H616 UART compatible for all six controllers so the driver can select their fixed 256-byte FIFO configuration and register layout. Retain the generic DesignWare compatible as a fallback for older kernels. Signed-off-by: James Hilliard --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index c6b3a3f8359a..b4b2f85726e0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -550,7 +550,7 @@ mmc2: mmc@4022000 { }; uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; + compatible = "allwinner,sun50i-h616-uart", "snps,dw-apb-uart"; reg = <0x05000000 0x400>; interrupts = ; reg-shift = <2>; @@ -563,7 +563,7 @@ uart0: serial@5000000 { }; uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; + compatible = "allwinner,sun50i-h616-uart", "snps,dw-apb-uart"; reg = <0x05000400 0x400>; interrupts = ; reg-shift = <2>; @@ -576,7 +576,7 @@ uart1: serial@5000400 { }; uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; + compatible = "allwinner,sun50i-h616-uart", "snps,dw-apb-uart"; reg = <0x05000800 0x400>; interrupts = ; reg-shift = <2>; @@ -589,7 +589,7 @@ uart2: serial@5000800 { }; uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; + compatible = "allwinner,sun50i-h616-uart", "snps,dw-apb-uart"; reg = <0x05000c00 0x400>; interrupts = ; reg-shift = <2>; @@ -602,7 +602,7 @@ uart3: serial@5000c00 { }; uart4: serial@5001000 { - compatible = "snps,dw-apb-uart"; + compatible = "allwinner,sun50i-h616-uart", "snps,dw-apb-uart"; reg = <0x05001000 0x400>; interrupts = ; reg-shift = <2>; @@ -615,7 +615,7 @@ uart4: serial@5001000 { }; uart5: serial@5001400 { - compatible = "snps,dw-apb-uart"; + compatible = "allwinner,sun50i-h616-uart", "snps,dw-apb-uart"; reg = <0x05001400 0x400>; interrupts = ; reg-shift = <2>;