[2/5] sunxi: H6: Remove useless DRAM timings parameter
Commit Message
This is just cosmetic fix for later easier rework.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 2 +-
arch/arm/mach-sunxi/dram_sun50i_h6.c | 2 +-
arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c | 2 +-
arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
@@ -330,6 +330,6 @@ static inline int ns_to_t(int nanoseconds)
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
-void mctl_set_timing_params(struct dram_para *para);
+void mctl_set_timing_params(void);
#endif /* _SUNXI_DRAM_SUN50I_H6_H */
@@ -45,7 +45,7 @@ static bool mctl_core_init(struct dram_para *para)
switch (para->type) {
case SUNXI_DRAM_TYPE_LPDDR3:
case SUNXI_DRAM_TYPE_DDR3:
- mctl_set_timing_params(para);
+ mctl_set_timing_params();
break;
default:
panic("Unsupported DRAM type!");
@@ -37,7 +37,7 @@ static u32 mr_ddr3[7] = {
};
/* TODO: flexible timing */
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(void)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
@@ -16,7 +16,7 @@ static u32 mr_lpddr3[12] = {
};
/* TODO: flexible timing */
-void mctl_set_timing_params(struct dram_para *para)
+void mctl_set_timing_params(void)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;