diff mbox series

[v13,3/3] riscv: dts: allwinner: d1: Add pwm node

Message ID 20260221183609.95403-4-privatesub2@gmail.com (mailing list archive)
State New
Headers
Series Add support for Allwinner PWM on D1/T113s/R329 SoCs |

Commit Message

Aleksandr Shubin Feb. 21, 2026, 6:35 p.m. UTC 
D1 and T113s contain a pwm controller with 8 channels.
This controller is supported by the sun8i-pwm driver.

Add a device tree node for it.

Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com>
---
 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Jernej Skrabec Feb. 22, 2026, 12:30 p.m. UTC | #1 
Dne sobota, 21. februar 2026 ob 19:35:53 Srednjeevropski standardni čas je Aleksandr Shubin napisal(a):
> D1 and T113s contain a pwm controller with 8 channels.
> This controller is supported by the sun8i-pwm driver.
> 
> Add a device tree node for it.
> 
> Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com>
> ---
>  arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> index 63e252b44973..8e38a0d95f5a 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -193,6 +193,19 @@ uart3_pb_pins: uart3-pb-pins {
>  			};
>  		};
>  
> +		pwm: pwm@2000c00 {
> +			compatible = "allwinner,sun20i-d1-pwm";
> +			reg = <0x02000c00 0x400>;
> +			clocks = <&ccu CLK_BUS_PWM>,
> +				 <&dcxo>,
> +				 <&ccu CLK_APB0>;
> +			clock-names = "bus", "hosc", "apb";
> +			resets = <&ccu RST_BUS_PWM>;
> +			status = "disabled";

Move status at the bottom.

> +			#pwm-cells = <0x3>;

Just use decimal format.

Best regards,
Jernej

> +			allwinner,npwms = <8>;
> +		};
> +
>  		ccu: clock-controller@2001000 {
>  			compatible = "allwinner,sun20i-d1-ccu";
>  			reg = <0x2001000 0x1000>;
>
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 63e252b44973..8e38a0d95f5a 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -193,6 +193,19 @@  uart3_pb_pins: uart3-pb-pins {
 			};
 		};
 
+		pwm: pwm@2000c00 {
+			compatible = "allwinner,sun20i-d1-pwm";
+			reg = <0x02000c00 0x400>;
+			clocks = <&ccu CLK_BUS_PWM>,
+				 <&dcxo>,
+				 <&ccu CLK_APB0>;
+			clock-names = "bus", "hosc", "apb";
+			resets = <&ccu RST_BUS_PWM>;
+			status = "disabled";
+			#pwm-cells = <0x3>;
+			allwinner,npwms = <8>;
+		};
+
 		ccu: clock-controller@2001000 {
 			compatible = "allwinner,sun20i-d1-ccu";
 			reg = <0x2001000 0x1000>;