[2/5] pinctrl: sunxi: Remove unneeded IRQ remuxing for some SoCs
Commit Message
The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
that line is muxed for IRQ triggering (muxval 6), but only if it's
explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
behaviour, so we added a optional workaround, triggered by a quirk bit,
which triggers remuxing the pin when it's configured for IRQ, while we
need to read its value.
For some reasons this quirk flag was copied over to newer SoCs, even
though they don't show this behaviour, and the GPIO data register
reflects the true GPIO state even with a pin configured to muxval 6
(IRQ). The workaround is just more costly, but doesn't break otherwise,
so this was probably never noticed by anyone.
Experiments confirm that the H5, H6, H616 and A523 do not need this
workaround, they show the GPIO line value with both muxval 0 and 6.
Remove the unneeded quirk from those SoC's pinctrl driver description.
This should have no obvious effect on the H5, H6, H616 (other than
being more efficient), but the workaround is broken for the A523, so
it fixes (one part of the) interrupt operation there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports")
---
drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 2 --
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 -
drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 1 -
drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 -
drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 1 -
5 files changed, 6 deletions(-)
Comments
On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
> that line is muxed for IRQ triggering (muxval 6), but only if it's
> explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
> behaviour, so we added a optional workaround, triggered by a quirk bit,
> which triggers remuxing the pin when it's configured for IRQ, while we
> need to read its value.
>
> For some reasons this quirk flag was copied over to newer SoCs, even
> though they don't show this behaviour, and the GPIO data register
> reflects the true GPIO state even with a pin configured to muxval 6
> (IRQ). The workaround is just more costly, but doesn't break otherwise,
> so this was probably never noticed by anyone.
> Experiments confirm that the H5, H6, H616 and A523 do not need this
> workaround, they show the GPIO line value with both muxval 0 and 6.
>
> Remove the unneeded quirk from those SoC's pinctrl driver description.
> This should have no obvious effect on the H5, H6, H616 (other than
> being more efficient), but the workaround is broken for the A523, so
> it fixes (one part of the) interrupt operation there.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports")
Acked-by: Chen-Yu Tsai <wens@kernel.org>
@@ -533,7 +533,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 2,
- .irq_read_needs_mux = true,
.disable_strict_mode = true,
};
@@ -541,7 +540,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 3,
- .irq_read_needs_mux = true,
.disable_strict_mode = true,
};
@@ -589,7 +589,6 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
.npins = ARRAY_SIZE(h6_pins),
.irq_banks = 4,
.irq_bank_map = h6_irq_bank_map,
- .irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};
@@ -875,7 +875,6 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
.npins = ARRAY_SIZE(h616_pins),
.irq_banks = ARRAY_SIZE(h616_irq_bank_map),
.irq_bank_map = h616_irq_bank_map,
- .irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
};
@@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {
.irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),
.irq_bank_map = a523_r_irq_bank_map,
- .irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
.pin_base = PL_BASE,
};
@@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
static struct sunxi_pinctrl_desc a523_pinctrl_data = {
.irq_banks = ARRAY_SIZE(a523_irq_bank_map),
.irq_bank_map = a523_irq_bank_map,
- .irq_read_needs_mux = true,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};