[v9,31/61] drm/rockchip: dw_hdmi_qp: Control the HPD IRQ line via the bridge HPD ops
| Message ID | 20260723-dw-hdmi-qp-scramb-v9-31-4fb12ea22ac9@collabora.com (mailing list archive) |
|---|---|
| State | New |
| Headers |
Return-Path: <linux-sunxi+bounces-24671-sunxi=pue.re@lists.linux.dev> X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 1A3941C2E7B for <noreply@patchwork.local>; Thu, 23 Jul 2026 03:37:04 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=collabora.com; spf=pass (sender IP is 172.232.135.74) smtp.mailfrom=linux-sunxi+bounces-24671-noreply=patchwork.local@lists.linux.dev smtp.helo=sto.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.232.135.74 as permitted sender) client-ip=172.232.135.74; envelope-from=linux-sunxi+bounces-24671-noreply=patchwork.local@lists.linux.dev; helo=sto.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sto.lore.kernel.org (Postfix) with ESMTP id 6171B30292C4 for <noreply@patchwork.local>; Thu, 23 Jul 2026 01:37:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4533B35C19D; Thu, 23 Jul 2026 01:35:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="oLapfbuR" X-Original-To: linux-sunxi@lists.linux.dev Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A0E4345740 for <linux-sunxi@lists.linux.dev>; Thu, 23 Jul 2026 01:35:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784770528; cv=none; b=lFF2U3djIz8t0WPMCX0KcPqVb4jykxynKi7KomVu3FMsWZrtjXghvRWersQnyJrnj7xHZQLhyyaRhLcxvHyjkyDo8nhJwbHA8ag/Q24/Vx+QRFid6p/k5MolFMSEtLLF3PmmRNAjQE2cK3D9bLCSboBh+3yXhzreldNgsk3kLwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784770528; c=relaxed/simple; bh=C/E1cpRXtqps6AVDXl0dbsrmxcX9GEPjGXzQ3d8wF4c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QfchUJQy4drsl3rNNQ1to/JAHiA/Z7Ib4rZGqmjcZTvlU/qWnEhi/Umcw1Iip57sjIZDi+xQaDP176H52Xj6VVXG3tY7XX+o7LIC7ldVjQBcvo5ujlTqjOoHdmoVITFQrwO2mrmUsrsX3DE8SYlr4Vu819ulJpsy4snT2DP+T5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=oLapfbuR; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784770523; bh=C/E1cpRXtqps6AVDXl0dbsrmxcX9GEPjGXzQ3d8wF4c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oLapfbuRLtYztsrD5ve5hhxebPuS6qd+1ltXvQFaP9tSBaKrl4JAY24a3G0U4zxTy mr+PfGTkRv45gHr8UoSvdtl1UfL2XR/QpdPD5cw7v7CGeWzeZ784Z5RV2DCG5LcoV0 QobWZ9bfWhDgq2R2zbYKFXYvJG8v3VwmQx5j+O/ikGGsUehUHDKKgFLG59TNbBcisV uo8VhjSz8XpXvT7KskzE+i6/1BpL0mS2WiE6YFivD723PhWMZ5NXq66ghPGafQQRSH 04gloFr3n6tYp9Ij9iT7Rg0pRoRGVGYpyAb8klJVdYTavagr+8CyvOzNY4ckV/p3n7 0Cw0K/EQyw5ug== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id BA0A117E023C; Thu, 23 Jul 2026 03:35:23 +0200 (CEST) From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Date: Thu, 23 Jul 2026 04:35:20 +0300 Subject: [PATCH v9 31/61] drm/rockchip: dw_hdmi_qp: Control the HPD IRQ line via the bridge HPD ops Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: <linux-sunxi.lists.linux.dev> List-Subscribe: <mailto:linux-sunxi+subscribe@lists.linux.dev> List-Unsubscribe: <mailto:linux-sunxi+unsubscribe@lists.linux.dev> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260723-dw-hdmi-qp-scramb-v9-31-4fb12ea22ac9@collabora.com> References: <20260723-dw-hdmi-qp-scramb-v9-0-4fb12ea22ac9@collabora.com> In-Reply-To: <20260723-dw-hdmi-qp-scramb-v9-0-4fb12ea22ac9@collabora.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Luca Ceresoli <luca.ceresoli@bootlin.com>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>, Chen-Yu Tsai <wens@kernel.org>, Samuel Holland <samuel@sholland.org>, Dave Stevenson <dave.stevenson@raspberrypi.com>, =?utf-8?q?Ma=C3=ADra_Canal?= <mcanal@igalia.com>, Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>, Sandy Huang <hjc@rock-chips.com>, =?utf-8?q?Heiko_St=C3=BCbner?= <heiko@sntech.de>, Andy Yan <andy.yan@rock-chips.com>, Algea Cao <algea.cao@rock-chips.com>, Daniel Stone <daniels@collabora.com>, Liu Ying <victor.liu@nxp.com>, Phong LE <ple@baylibre.com> Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-rockchip@lists.infradead.org X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= |
| Series |
Add HDMI 2.0 support to DW HDMI QP TX
|
|
Commit Message
Cristian Ciocaltea
July 23, 2026, 1:35 a.m. UTC
The HPD interrupt must not be delivered before the DRM connector is fully
set up, and it should be quiesced while the display pipeline is suspended.
On top of that, the threaded handler re-arms HPD unconditionally after the
hotplug debounce, which must not override an explicit disable requested by
the DRM core.
Request the HPD IRQ in bind() with IRQF_NO_AUTOEN so it stays disabled
until the core arms it, and drive enable_irq()/disable_irq() from the
phy ops invoked by the bridge through its hpd_{enable,disable}()
callbacks. This ensures the line is only armed after the connector is
ready. disable_irq() additionally waits for the threaded handler to
finish, so its GRF re-arm can no longer race with and override a
core-requested disable.
Note that IRQF_NO_AUTOEN is incompatible with IRQF_SHARED; the latter is
dropped as this IRQ has no other users.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
Comments
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Delayed HPD work is not cancelled when HPD is disabled, risking execution while the display pipeline is suspended or disabled.
--
--- Patch [31]: [PATCH v9 31/61] drm/rockchip: dw_hdmi_qp: Control the HPD IRQ line via the bridge HPD ops ---
commit 1832550496f2064373166520bd5d2d00accd260b
Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
drm/rockchip: dw_hdmi_qp: Control the HPD IRQ line via the bridge HPD ops
This commit changes the HPD interrupt handling to request it with
IRQF_NO_AUTOEN and enables/disables it dynamically through the bridge
hpd_{enable,disable}() callbacks.
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> index cdddbbb8b80b2..534a2c8da2a0a 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
[ ... ]
> @@ -308,12 +309,14 @@ static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
> struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
>
> dw_hdmi_qp_rk3588_unmask_hpd(hdmi);
> + enable_irq(hdmi->hpd_irq);
> }
>
> static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
> {
> struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
>
> + disable_irq(hdmi->hpd_irq);
[Severity: High]
This isn't a bug introduced by this patch, but does this leave the scheduled
delayed work running?
When the DRM core disables HPD during suspend, disable_irq() waits for the
threaded interrupt handler to finish, but the scheduled hdmi->hpd_work is not
cancelled. If an HPD interrupt occurs right before suspend, the delayed work
might execute 150ms later while the display pipeline is suspended or disabled.
Could this access hardware registers (like GRF) after clocks or power domains
have been disabled, and cause a system hang? Would it be safer to add
cancel_delayed_work_sync(&hdmi->hpd_work) here in the disable callbacks, or in
dw_hdmi_qp_rockchip_suspend()?
> dw_hdmi_qp_rk3588_mask_hpd(hdmi);
> }
[ ... ]
> static void dw_hdmi_qp_rk3576_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
> {
> struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
>
> + disable_irq(hdmi->hpd_irq);
[Severity: High]
This isn't a bug introduced by this patch, but this has the same issue with
uncancelled delayed work as the rk3588 variant above.
> dw_hdmi_qp_rk3576_mask_hpd(hdmi);
> }
>
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c index cdddbbb8b80b..534a2c8da2a0 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -99,6 +99,7 @@ struct rockchip_hdmi_qp { struct phy *phy; struct gpio_desc *frl_enable_gpio; struct delayed_work hpd_work; + int hpd_irq; int port_id; const struct rockchip_hdmi_qp_ctrl_ops *ctrl_ops; unsigned long long tmds_char_rate; @@ -308,12 +309,14 @@ static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; dw_hdmi_qp_rk3588_unmask_hpd(hdmi); + enable_irq(hdmi->hpd_irq); } static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + disable_irq(hdmi->hpd_irq); dw_hdmi_qp_rk3588_mask_hpd(hdmi); } @@ -355,12 +358,14 @@ static void dw_hdmi_qp_rk3576_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; dw_hdmi_qp_rk3576_unmask_hpd(hdmi); + enable_irq(hdmi->hpd_irq); } static void dw_hdmi_qp_rk3576_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + disable_irq(hdmi->hpd_irq); dw_hdmi_qp_rk3576_mask_hpd(hdmi); } @@ -584,7 +589,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, struct resource *res; struct clk_bulk_data *clks; struct clk *ref_clk; - int ret, irq, i; + int ret, i; if (!dev->of_node) return -ENODEV; @@ -688,14 +693,14 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, if (plat_data.cec_irq < 0) return plat_data.cec_irq; - irq = platform_get_irq_byname(pdev, "hpd"); - if (irq < 0) - return irq; + hdmi->hpd_irq = platform_get_irq_byname(pdev, "hpd"); + if (hdmi->hpd_irq < 0) + return hdmi->hpd_irq; - ret = devm_request_threaded_irq(dev, irq, + ret = devm_request_threaded_irq(dev, hdmi->hpd_irq, cfg->ctrl_ops->hardirq_callback, cfg->ctrl_ops->irq_callback, - IRQF_SHARED, "dw-hdmi-qp-hpd", + IRQF_NO_AUTOEN, "dw-hdmi-qp-hpd", hdmi); if (ret) return ret;