From: Richard Genoud <richard.genoud@bootlin.com>
The H616 secondary EMAC uses a separate system-control clock register
and supports only RMII at 10/100 Mbps. Add its distinct compatible
without an older fallback, since using the primary EMAC clock register
would not work.
Constrain the PHY interface mode to RMII, matching the hardware. The
EMAC1 clock register also retains the three-bit TX and five-bit RX delay
chains, so allow the existing Allwinner delay properties for this
compatible.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
---
.../bindings/net/allwinner,sun8i-a83t-emac.yaml | 18 ++++++++++++++++--
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 ++
2 files changed, 18 insertions(+), 2 deletions(-)
> Constrain the PHY interface mode to RMII, matching the hardware. The
> EMAC1 clock register also retains the three-bit TX and five-bit RX delay
> chains, so allow the existing Allwinner delay properties for this
> compatible.
The delay properties are for RGMII, not RMII. What do they actually do
when used with RMII?
Andrew
@@ -21,6 +21,7 @@ select:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
- allwinner,sun55i-a523-gmac200
required:
- compatible
@@ -33,6 +34,7 @@ properties:
- const: allwinner,sun8i-r40-gmac
- const: allwinner,sun8i-v3s-emac
- const: allwinner,sun50i-a64-emac
+ - const: allwinner,sun50i-h616-emac1
- items:
- enum:
- allwinner,sun20i-d1-emac
@@ -91,6 +93,17 @@ required:
allOf:
- $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h616-emac1
+
+ then:
+ properties:
+ phy-mode:
+ const: rmii
+
- if:
properties:
compatible:
@@ -100,6 +113,7 @@ allOf:
- allwinner,sun8i-h3-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
then:
properties:
@@ -109,7 +123,7 @@ allOf:
maximum: 700
multipleOf: 100
description:
- External RGMII PHY TX clock delay chain value in ps.
+ PHY interface TX clock delay chain value in ps.
allwinner,rx-delay-ps:
default: 0
@@ -117,7 +131,7 @@ allOf:
maximum: 3100
multipleOf: 100
description:
- External RGMII PHY TX clock delay chain value in ps.
+ PHY interface RX clock delay chain value in ps.
- if:
properties:
@@ -57,6 +57,7 @@ properties:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
@@ -622,6 +623,7 @@ allOf:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
- ingenic,jz4775-mac