[net-next,v3,1/3] net: stmmac: sun8i: reset the MAC after PHY initialization
Commit Message
The MAC software reset needs a running receive clock from the PHY.
Resetting the MAC at the end of probe therefore fails when the PHY driver
has not been loaded or its probe has deferred on a missing supplier. The
failure removes the MAC and its MDIO bus, so loading the missing driver
later cannot recover the interface without reprobing the MAC.
Perform the software reset in the DMA reset callback instead. The stmmac
core calls it during hardware setup after attaching and initializing the
PHY, and resumes a suspended PHY before reopening or resuming the MAC.
Keep the existing register clearing after a successful reset and return
reset errors through the normal hardware-setup error path.
Remove the unconditional reset from probe. Keep the separate H3 MDIO-mux
reset after switching the mux and powering the selected PHY, since it is
needed to latch the selected interface before MDIO accesses.
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 50 +++++++++++------------
1 file changed, 24 insertions(+), 26 deletions(-)
Comments
Hi,
On 9/17/26 19:55, James Hilliard wrote:
> The MAC software reset needs a running receive clock from the PHY.
> Resetting the MAC at the end of probe therefore fails when the PHY driver
> has not been loaded or its probe has deferred on a missing supplier. The
> failure removes the MAC and its MDIO bus, so loading the missing driver
> later cannot recover the interface without reprobing the MAC.
>
> Perform the software reset in the DMA reset callback instead. The stmmac
> core calls it during hardware setup after attaching and initializing the
> PHY, and resumes a suspended PHY before reopening or resuming the MAC.
> Keep the existing register clearing after a successful reset and return
> reset errors through the normal hardware-setup error path.
>
> Remove the unconditional reset from probe. Keep the separate H3 MDIO-mux
> reset after switching the mux and powering the selected PHY, since it is
> needed to latch the selected interface before MDIO accesses.
>
> Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Maxime
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 50 +++++++++++------------
> 1 file changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> index 48c52eb96233..4523a14f5e0c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> @@ -269,11 +269,32 @@ static const struct emac_variant emac_variant_h6 = {
> #define SYSCON_ETCS_EXT_GMII 0x1
> #define SYSCON_ETCS_INT_GMII 0x2
>
> +static int sun8i_dwmac_reset(void __iomem *ioaddr)
> +{
> + u32 v;
> +
> + v = readl(ioaddr + EMAC_BASIC_CTL1);
> + writel(v | 0x01, ioaddr + EMAC_BASIC_CTL1);
> +
> + /* The timeout was previously set to 10ms, but some board (OrangePI0)
> + * need more if no cable plugged. 100ms seems OK
> + */
> + return readl_poll_timeout(ioaddr + EMAC_BASIC_CTL1, v,
> + !(v & 0x01), 100, 100000);
> +}
> +
> /* sun8i_dwmac_dma_reset() - reset the EMAC
> * Called from stmmac via stmmac_dma_ops->reset
> */
> static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
> {
> + int ret;
> +
> + /* The PHY receive clock must be running for the reset to complete. */
> + ret = sun8i_dwmac_reset(ioaddr);
> + if (ret)
> + return ret;
> +
> writel(0, ioaddr + EMAC_RX_CTL1);
> writel(0, ioaddr + EMAC_TX_CTL1);
> writel(0, ioaddr + EMAC_RX_FRM_FLT);
> @@ -738,27 +759,6 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
> writel(v, ioaddr + EMAC_TX_FLOW_CTL);
> }
>
> -static int sun8i_dwmac_reset(struct stmmac_priv *priv)
> -{
> - u32 v;
> - int err;
> -
> - v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
> - writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
> -
> - /* The timeout was previously set to 10ms, but some board (OrangePI0)
> - * need more if no cable plugged. 100ms seems OK
> - */
> - err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
> - !(v & 0x01), 100, 100000);
> -
> - if (err) {
> - dev_err(priv->device, "EMAC reset timeout\n");
> - return err;
> - }
> - return 0;
> -}
> -
> /* Search in mdio-mux node for internal PHY node and get its clk/reset */
> static int get_ephy_nodes(struct stmmac_priv *priv)
> {
> @@ -895,7 +895,9 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
> /* After changing syscon value, the MAC need reset or it will
> * use the last value (and so the last PHY set).
> */
> - ret = sun8i_dwmac_reset(priv);
> + ret = sun8i_dwmac_reset(priv->ioaddr);
> + if (ret)
> + dev_err(priv->device, "EMAC reset timeout\n");
> }
> return ret;
> }
> @@ -1217,10 +1219,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
> dev_err(&pdev->dev, "Failed to register mux\n");
> goto dwmac_mux;
> }
> - } else {
> - ret = sun8i_dwmac_reset(priv);
> - if (ret)
> - goto dwmac_remove;
> }
>
> pm_runtime_put(&pdev->dev);
>
@@ -269,11 +269,32 @@ static const struct emac_variant emac_variant_h6 = {
#define SYSCON_ETCS_EXT_GMII 0x1
#define SYSCON_ETCS_INT_GMII 0x2
+static int sun8i_dwmac_reset(void __iomem *ioaddr)
+{
+ u32 v;
+
+ v = readl(ioaddr + EMAC_BASIC_CTL1);
+ writel(v | 0x01, ioaddr + EMAC_BASIC_CTL1);
+
+ /* The timeout was previously set to 10ms, but some board (OrangePI0)
+ * need more if no cable plugged. 100ms seems OK
+ */
+ return readl_poll_timeout(ioaddr + EMAC_BASIC_CTL1, v,
+ !(v & 0x01), 100, 100000);
+}
+
/* sun8i_dwmac_dma_reset() - reset the EMAC
* Called from stmmac via stmmac_dma_ops->reset
*/
static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
{
+ int ret;
+
+ /* The PHY receive clock must be running for the reset to complete. */
+ ret = sun8i_dwmac_reset(ioaddr);
+ if (ret)
+ return ret;
+
writel(0, ioaddr + EMAC_RX_CTL1);
writel(0, ioaddr + EMAC_TX_CTL1);
writel(0, ioaddr + EMAC_RX_FRM_FLT);
@@ -738,27 +759,6 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
writel(v, ioaddr + EMAC_TX_FLOW_CTL);
}
-static int sun8i_dwmac_reset(struct stmmac_priv *priv)
-{
- u32 v;
- int err;
-
- v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
- writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
-
- /* The timeout was previously set to 10ms, but some board (OrangePI0)
- * need more if no cable plugged. 100ms seems OK
- */
- err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
- !(v & 0x01), 100, 100000);
-
- if (err) {
- dev_err(priv->device, "EMAC reset timeout\n");
- return err;
- }
- return 0;
-}
-
/* Search in mdio-mux node for internal PHY node and get its clk/reset */
static int get_ephy_nodes(struct stmmac_priv *priv)
{
@@ -895,7 +895,9 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
/* After changing syscon value, the MAC need reset or it will
* use the last value (and so the last PHY set).
*/
- ret = sun8i_dwmac_reset(priv);
+ ret = sun8i_dwmac_reset(priv->ioaddr);
+ if (ret)
+ dev_err(priv->device, "EMAC reset timeout\n");
}
return ret;
}
@@ -1217,10 +1219,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "Failed to register mux\n");
goto dwmac_mux;
}
- } else {
- ret = sun8i_dwmac_reset(priv);
- if (ret)
- goto dwmac_remove;
}
pm_runtime_put(&pdev->dev);