@@ -88,7 +88,7 @@ static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
plat_dat->core_type = DWMAC_CORE_GMAC4;
plat_dat->dma_cfg->aal = 1;
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
- plat_dat->pmt = 1;
+ plat_dat->pmt = true;
return 0;
}
@@ -566,7 +566,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->clk_csr = STMMAC_CSR_20_35M;
plat->core_type = DWMAC_CORE_GMAC;
- plat->force_sf_dma_mode = 1;
+ plat->force_sf_dma_mode = true;
plat->mdio_bus_data->needs_reset = true;
}
@@ -94,7 +94,7 @@ static void loongson_default_data(struct pci_dev *pdev,
/* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
plat->clk_csr = STMMAC_CSR_100_150M;
plat->core_type = DWMAC_CORE_GMAC;
- plat->force_sf_dma_mode = 1;
+ plat->force_sf_dma_mode = true;
/* Increase the default value for multicast hash bins */
plat->multicast_filter_bins = 256;
@@ -564,7 +564,7 @@ static int mediatek_dwmac_common_data(struct platform_device *pdev,
plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL;
else
plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
- plat->riwt_off = 1;
+ plat->riwt_off = true;
plat->maxmtu = ETH_DATA_LEN;
plat->host_dma_width = priv_plat->variant->dma_bit_mask;
plat->bsp_priv = priv_plat;
@@ -817,7 +817,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
plat_dat->core_type = DWMAC_CORE_GMAC4;
if (ethqos->has_emac_ge_3)
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
- plat_dat->pmt = 1;
+ plat_dat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
@@ -163,7 +163,7 @@ static int s32_dwmac_probe(struct platform_device *pdev)
/* S32CC core feature set */
plat->core_type = DWMAC_CORE_GMAC4;
- plat->pmt = 1;
+ plat->pmt = true;
plat->flags |= STMMAC_FLAG_SPH_DISABLE;
plat->rx_fifo_size = 20480;
plat->tx_fifo_size = 20480;
@@ -565,7 +565,7 @@ static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
plat_dat->core_type = DWMAC_CORE_GMAC;
/* Rx watchdog timer in dwmac is buggy in this hw */
- plat_dat->riwt_off = 1;
+ plat_dat->riwt_off = true;
}
static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
@@ -1179,7 +1179,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
* hardware features were copied from Allwinner drivers.
*/
plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
- plat_dat->tx_coe = 1;
+ plat_dat->tx_coe = true;
plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
plat_dat->bsp_priv = gmac;
plat_dat->init = sun8i_dwmac_init;
@@ -135,7 +135,7 @@ static int sun7i_gmac_probe(struct platform_device *pdev)
/* platform data specifying hardware features and callbacks.
* hardware features were copied from Allwinner drivers. */
- plat_dat->tx_coe = 1;
+ plat_dat->tx_coe = true;
plat_dat->core_type = DWMAC_CORE_GMAC;
plat_dat->bsp_priv = gmac;
plat_dat->init = sun7i_gmac_init;
@@ -310,7 +310,7 @@ static int tegra_mgbe_probe(struct platform_device *pdev)
plat->core_type = DWMAC_CORE_XGMAC;
plat->flags |= STMMAC_FLAG_TSO_EN;
- plat->pmt = 1;
+ plat->pmt = true;
plat->bsp_priv = mgbe;
if (!plat->mdio_node)
@@ -7401,7 +7401,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
/* TXCOE doesn't work in thresh DMA mode */
if (priv->plat->force_thresh_dma_mode)
- priv->plat->tx_coe = 0;
+ priv->plat->tx_coe = false;
else
priv->plat->tx_coe = priv->dma_cap.tx_coe;
@@ -25,7 +25,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->clk_csr = STMMAC_CSR_20_35M;
plat->core_type = DWMAC_CORE_GMAC;
- plat->force_sf_dma_mode = 1;
+ plat->force_sf_dma_mode = true;
plat->mdio_bus_data->needs_reset = true;
}
@@ -58,9 +58,9 @@ static int snps_gmac5_default_data(struct pci_dev *pdev,
plat->clk_csr = STMMAC_CSR_250_300M;
plat->core_type = DWMAC_CORE_GMAC4;
- plat->force_sf_dma_mode = 1;
+ plat->force_sf_dma_mode = true;
plat->flags |= STMMAC_FLAG_TSO_EN;
- plat->pmt = 1;
+ plat->pmt = true;
/* Set default number of RX and TX queues to use */
plat->tx_queues_to_use = 4;
@@ -514,34 +514,34 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)
plat->multicast_filter_bins = dwmac1000_validate_mcast_bins(
&pdev->dev, plat->multicast_filter_bins);
plat->core_type = DWMAC_CORE_GMAC;
- plat->pmt = 1;
+ plat->pmt = true;
}
if (of_device_is_compatible(np, "snps,dwmac-3.40a")) {
plat->core_type = DWMAC_CORE_GMAC;
- plat->enh_desc = 1;
- plat->tx_coe = 1;
- plat->bugged_jumbo = 1;
- plat->pmt = 1;
+ plat->enh_desc = true;
+ plat->tx_coe = true;
+ plat->bugged_jumbo = true;
+ plat->pmt = true;
}
if (of_device_compatible_match(np, stmmac_gmac4_compats)) {
plat->core_type = DWMAC_CORE_GMAC4;
- plat->pmt = 1;
+ plat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat->flags |= STMMAC_FLAG_TSO_EN;
}
if (of_device_is_compatible(np, "snps,dwmac-3.610") ||
of_device_is_compatible(np, "snps,dwmac-3.710")) {
- plat->enh_desc = 1;
- plat->bugged_jumbo = 1;
- plat->force_sf_dma_mode = 1;
+ plat->enh_desc = true;
+ plat->bugged_jumbo = true;
+ plat->force_sf_dma_mode = true;
}
if (of_device_is_compatible(np, "snps,dwxgmac")) {
plat->core_type = DWMAC_CORE_XGMAC;
- plat->pmt = 1;
+ plat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat->flags |= STMMAC_FLAG_TSO_EN;
of_property_read_u32(np, "snps,multicast-filter-bins",
@@ -229,14 +229,14 @@ struct plat_stmmacenet_data {
struct stmmac_dma_cfg *dma_cfg;
struct stmmac_safety_feature_cfg *safety_feat_cfg;
int clk_csr;
- int enh_desc;
- int tx_coe;
+ bool enh_desc;
+ bool tx_coe;
+ bool bugged_jumbo;
+ bool pmt;
+ bool force_sf_dma_mode;
+ bool force_thresh_dma_mode;
+ bool riwt_off;
int rx_coe;
- int bugged_jumbo;
- int pmt;
- int force_sf_dma_mode;
- int force_thresh_dma_mode;
- int riwt_off;
int max_speed;
int maxmtu;
int multicast_filter_bins;