[net-next,1/2] dt-bindings: net: allwinner: add H616 EMAC1
Commit Message
The H616 secondary EMAC uses a separate system-control clock register
and supports only RMII at 10/100 Mbps. Add its distinct compatible
without an older fallback, since using the primary EMAC clock register
would not work.
Constrain the PHY interface mode to RMII, matching the hardware. The
EMAC1 clock register also retains the three-bit TX and five-bit RX delay
chains, so allow the existing Allwinner delay properties for this
compatible.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
---
.../bindings/net/allwinner,sun8i-a83t-emac.yaml | 18 ++++++++++++++++--
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 ++
2 files changed, 18 insertions(+), 2 deletions(-)
Comments
Hi James,
On 9/15/26 21:03, James Hilliard wrote:
> The H616 secondary EMAC uses a separate system-control clock register
> and supports only RMII at 10/100 Mbps. Add its distinct compatible
> without an older fallback, since using the primary EMAC clock register
> would not work.
>
> Constrain the PHY interface mode to RMII, matching the hardware. The
> EMAC1 clock register also retains the three-bit TX and five-bit RX delay
> chains, so allow the existing Allwinner delay properties for this
> compatible.
I don't think there's such a thing as RMII delays. RMII has a single
clock, contrary to RGMII that has a TX and a RX clock with a 2ns delay
between clock and data.
I think it's just a leftover in this IP from the other variants that
can do RGMII ? You should just be able to drop the comment changes here,
and same goes for the dwmac patch.
Maxime
On Tue, Sep 15, 2026 at 10:33:12PM +0200, Maxime Chevallier wrote:
> Hi James,
>
> On 9/15/26 21:03, James Hilliard wrote:
> > The H616 secondary EMAC uses a separate system-control clock register
> > and supports only RMII at 10/100 Mbps. Add its distinct compatible
> > without an older fallback, since using the primary EMAC clock register
> > would not work.
> >
> > Constrain the PHY interface mode to RMII, matching the hardware. The
> > EMAC1 clock register also retains the three-bit TX and five-bit RX delay
> > chains, so allow the existing Allwinner delay properties for this
> > compatible.
>
> I don't think there's such a thing as RMII delays. RMII has a single
> clock, contrary to RGMII that has a TX and a RX clock with a 2ns delay
> between clock and data.
>
> I think it's just a leftover in this IP from the other variants that
> can do RGMII ? You should just be able to drop the comment changes here,
> and same goes for the dwmac patch.
That was my thinking as well.
Andrew
On Tue, Sep 15, 2026 at 2:33 PM Maxime Chevallier
<maxime.chevallier@bootlin.com> wrote:
>
> Hi James,
>
> On 9/15/26 21:03, James Hilliard wrote:
> > The H616 secondary EMAC uses a separate system-control clock register
> > and supports only RMII at 10/100 Mbps. Add its distinct compatible
> > without an older fallback, since using the primary EMAC clock register
> > would not work.
> >
> > Constrain the PHY interface mode to RMII, matching the hardware. The
> > EMAC1 clock register also retains the three-bit TX and five-bit RX delay
> > chains, so allow the existing Allwinner delay properties for this
> > compatible.
>
> I don't think there's such a thing as RMII delays. RMII has a single
> clock, contrary to RGMII that has a TX and a RX clock with a 2ns delay
> between clock and data.
>
> I think it's just a leftover in this IP from the other variants that
> can do RGMII ? You should just be able to drop the comment changes here,
> and same goes for the dwmac patch.
Yeah, looks like most but not all vendor driver variants had RMII delays
configured here, I did test and it doesn't seem to be needed so I went
ahead and dropped the delays in my v2. So yeah, seems to have been
just a leftover config.
>
> Maxime
>
@@ -21,6 +21,7 @@ select:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
- allwinner,sun55i-a523-gmac200
required:
- compatible
@@ -33,6 +34,7 @@ properties:
- const: allwinner,sun8i-r40-gmac
- const: allwinner,sun8i-v3s-emac
- const: allwinner,sun50i-a64-emac
+ - const: allwinner,sun50i-h616-emac1
- items:
- enum:
- allwinner,sun20i-d1-emac
@@ -91,6 +93,17 @@ required:
allOf:
- $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h616-emac1
+
+ then:
+ properties:
+ phy-mode:
+ const: rmii
+
- if:
properties:
compatible:
@@ -100,6 +113,7 @@ allOf:
- allwinner,sun8i-h3-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
then:
properties:
@@ -109,7 +123,7 @@ allOf:
maximum: 700
multipleOf: 100
description:
- External RGMII PHY TX clock delay chain value in ps.
+ PHY interface TX clock delay chain value in ps.
allwinner,rx-delay-ps:
default: 0
@@ -117,7 +131,7 @@ allOf:
maximum: 3100
multipleOf: 100
description:
- External RGMII PHY TX clock delay chain value in ps.
+ PHY interface RX clock delay chain value in ps.
- if:
properties:
@@ -57,6 +57,7 @@ properties:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
@@ -623,6 +624,7 @@ allOf:
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - allwinner,sun50i-h616-emac1
- loongson,ls2k-dwmac
- loongson,ls7a-dwmac
- ingenic,jz4775-mac