[net-next,v2,5/7] net: stmmac: use u8 for host_dma_width and similar struct members
Commit Message
We aren't going to see >= 256-bit address busses soon, so reduce
host_dma_width and associated other struct members that initialise
this from u32 to u8.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 6 +++---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 2 +-
include/linux/stmmac.h | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
Comments
On Mon, Mar 09, 2026 at 09:39:39AM +0000, Russell King (Oracle) wrote:
> We aren't going to see >= 256-bit address busses soon, so reduce
> host_dma_width and associated other struct members that initialise
> this from u32 to u8.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 2 +-
> drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 6 +++---
> drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 2 +-
> include/linux/stmmac.h | 2 +-
> 4 files changed, 6 insertions(+), 6 deletions(-)
>
Acked-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> # qcom-ethqos
@@ -42,8 +42,8 @@
struct imx_priv_data;
struct imx_dwmac_ops {
- u32 addr_width;
u32 flags;
+ u8 addr_width;
bool mac_rgmii_txclk_auto_adj;
int (*fix_soc_reset)(struct stmmac_priv *priv);
@@ -93,9 +93,9 @@ struct mediatek_dwmac_variant {
const char * const *clk_list;
int num_clks;
- u32 dma_bit_mask;
u32 rx_delay_max;
u32 tx_delay_max;
+ u8 dma_bit_mask;
};
/* list of clocks required for mac */
@@ -268,9 +268,9 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
.dwmac_set_delay = mt2712_set_delay,
.clk_list = mt2712_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
- .dma_bit_mask = 33,
.rx_delay_max = 17600,
.tx_delay_max = 17600,
+ .dma_bit_mask = 33,
};
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
@@ -418,9 +418,9 @@ static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
.dwmac_set_delay = mt8195_set_delay,
.clk_list = mt8195_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
- .dma_bit_mask = 35,
.rx_delay_max = 9280,
.tx_delay_max = 9280,
+ .dma_bit_mask = 35,
};
static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
@@ -91,8 +91,8 @@ struct ethqos_emac_driver_data {
unsigned int num_rgmii_por;
bool rgmii_config_loopback_en;
bool has_emac_ge_3;
+ u8 dma_addr_width;
const char *link_clk_name;
- u32 dma_addr_width;
struct dwmac4_addrs dwmac4_addrs;
bool needs_sgmii_loopback;
};
@@ -243,7 +243,7 @@ struct plat_stmmacenet_data {
int unicast_filter_entries;
int tx_fifo_size;
int rx_fifo_size;
- u32 host_dma_width;
+ u8 host_dma_width;
u8 rx_queues_to_use;
u8 tx_queues_to_use;
u8 rx_sched_algorithm;