| Message ID | 20260917223913.1855301-1-andre.przywara@arm.com (mailing list archive) |
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(usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 123933F86F; Thu, 17 Sep 2026 15:39:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789684765; bh=zSr8ucmt3atALw0jtcqHgXRhkY4eSjq6WuvhwB16jkI=; h=From:To:Cc:Subject:Date:From; b=q+OIDnTe72k1qtLdZwBjc+pT9GJ0hOyYW/n74h9zlWlFJg80CSBewedTn42BRsOgX IEchLZjZHllmaMdaLn7bVQdyvfbPXnrB+QavRKytYAydIch75lCMy/69LSMRadAyYF 20VE9ZABdqWJeAuDySAaVxoEdXYq+FHER8M2XkDc= From: Andre Przywara <andre.przywara@arm.com> To: Stephen Boyd <sboyd@kernel.org>, Brian Masney <bmasney+clk@redhat.com>, Jerome Brunet <jbrunet+clk@baylibre.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@kernel.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org> Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH v2 0/5] arm64: allwinner: a523: Enable CPU clocks Date: Fri, 18 Sep 2026 00:39:08 +0200 Message-ID: <20260917223913.1855301-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: <linux-sunxi.lists.linux.dev> List-Subscribe: <mailto:linux-sunxi+subscribe@lists.linux.dev> List-Unsubscribe: <mailto:linux-sunxi+unsubscribe@lists.linux.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[104.64.211.4:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; TAGGED_RCPT(0.00)[clk,dt]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[arm.com:dkim,sin.lore.kernel.org:rdns,sin.lore.kernel.org:helo]; RCPT_COUNT_TWELVE(0.00)[13]; FORGED_SENDER_MAILLIST(0.00)[]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; R_SPF_ALLOW(0.00)[+ip4:104.64.211.4]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received]; TO_DN_SOME(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26021-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:104.64.192.0/19, country:SG]; RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[104.64.211.4:from] X-Rspamd-Queue-Id: 7782B1C29A4 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= |
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arm64: allwinner: a523: Enable CPU clocks
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Message
Andre Przywara
Sept. 17, 2026, 10:39 p.m. UTC
Hi, after a year (again?) an update to the A523 CPU clock series. I heeded Chen-Yu's advice and generalised the update bit to cover both the "key" use case and the now no longer fixed update bit (patch 1). I also followed one of Krzysztof's suggestions around the binding headers. For a changelog see below. Based on v7.3-rc1. This clashes slightly with the already queued clock fixes from Junhui, please let me know how I should play this. ============================== This series adds support for the CPU clock controller in the Allwinner A523/A527/T527 family of SoCs. In contrast to all earlier Allwinner SoCs, this chip features a separate CCU for the CPU clocks (one for each of the two clusters) and the DSU clock. Patches 1 and 2 add some slight enhancements to the sunxi-ng clock driver framework, to generalise the update bit and allow clocks with just a power-of-2 divider. Patch 3 adds the binding document for the new CCU. Patch 4 adds the actual clock driver, and patch 5 makes use of that by adding the clock description to the SoC .dtsi. Please have a look and test! Cheers, Andre Changes in v2: - rebase on v7.3-rc1 - cover CCU_FEATURE_KEY_FIELD in update bits generalisation - explicitly include binding header in clock driver - order clocks property before enable-method in DT nodes Andre Przywara (5): clk: sunxi-ng: generalise update bit clk: sunxi-ng: mp: support clocks with just a shift register dt-bindings: clock: sun55i-a523-ccu: Add A523 CPU CCU clock controller clk: sunxi-ng: add support for the A523/T527 CPU CCU arm64: dts: allwinner: a523: add CPU clocks .../clock/allwinner,sun55i-a523-ccu.yaml | 25 ++ .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 22 ++ drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun55i-a523-cpu.c | 340 ++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun55i-a523-cpu.h | 24 ++ drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 12 +- drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 4 +- drivers/clk/sunxi-ng/ccu_common.h | 8 +- drivers/clk/sunxi-ng/ccu_div.c | 3 +- drivers/clk/sunxi-ng/ccu_gate.c | 6 +- drivers/clk/sunxi-ng/ccu_mp.c | 6 +- drivers/clk/sunxi-ng/ccu_mp.h | 8 +- drivers/clk/sunxi-ng/ccu_mux.c | 8 +- drivers/clk/sunxi-ng/ccu_nm.c | 1 + .../dt-bindings/clock/sun55i-a523-cpu-ccu.h | 13 + 16 files changed, 456 insertions(+), 31 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523-cpu.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523-cpu.h create mode 100644 include/dt-bindings/clock/sun55i-a523-cpu-ccu.h base-commit: cee9395acd8043be0644b25c34bfa86623f2b935