[v2,5/5] arm64: dts: allwinner: a523: add CPU clocks
Commit Message
The Allwinner A523 family of SoCs feature a separate clock unit for the
CPU PLLs and muxes, including one for the DSU interconnect.
Add a DT node for the CPU clock controller, and list all the clocks from
the other CCUs that this controller needs.
Also list the clock source for each CPU: there is one clock for each
cluster of four cores, suffixed L and B, for little and big (although
all cores are of the same Cortex-A55 type).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
Comments
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt: sun55i-a523: incorrect #reset-cells in cpu_ccu
- [Low] dt: sun55i-a523: clock-names mismatch pll-periph0-600M
--
commit e064b2e2cf12882a6bab40a91b6eb61a493b3e06
Author: Andre Przywara <andre.przywara@arm.com>
arm64: dts: allwinner: a523: add CPU clocks
The Allwinner A523 family of SoCs feature a separate clock unit for the CPU
PLLs and muxes. This patch adds a DT node for the CPU clock controller and
lists the required clocks and sources for each CPU.
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> index 85ef492ffeae7..29af21372aba2 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
[ ... ]
> @@ -1144,5 +1153,18 @@ npu: npu@7122000 {
> resets = <&mcu_ccu RST_BUS_MCU_NPU>;
> power-domains = <&ppu PD_NPU>;
> };
> +
> + cpu_ccu: clock-controller@8817000 {
> + compatible = "allwinner,sun55i-a523-cpu-ccu";
> + reg = <0x08817000 0x80>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0_2X>,
> + <&ccu CLK_PLL_PERIPH0_600M>;
> + clock-names = "hosc", "losc",
> + "iosc", "pll-periph0-2x",
> + "pll-periph0-600M";
[Severity: Low]
Will this clock name cause a validation regression during dtbs_check?
In the cpu_ccu node of arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi, the
device tree uses pll-periph0-600M. This matches the driver, but the YAML
binding strictly expects pll-periph0-600m.
This case mismatch will fail validation when running make dtbs_check.
> + #clock-cells = <1>;
> + #reset-cells = <1>;
[Severity: Low]
Does this introduce a regression in the DT description by erroneously declaring
cpu_ccu as a reset controller provider?
The #reset-cells = <1> property in the cpu_ccu node describes it as a reset
controller, but the hardware and driver do not provide resets.
This appears to be satisfying a flawed YAML binding that erroneously mandates
it globally for all compatibles.
> + };
> };
> };
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/sun55i-a523-ccu.h>
#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
+#include <dt-bindings/clock/sun55i-a523-cpu-ccu.h>
#include <dt-bindings/reset/sun55i-a523-ccu.h>
#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
@@ -25,6 +26,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x000>;
+ clocks = <&cpu_ccu CLK_CPU_L>;
enable-method = "psci";
};
@@ -32,6 +34,7 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x100>;
+ clocks = <&cpu_ccu CLK_CPU_L>;
enable-method = "psci";
};
@@ -39,6 +42,7 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x200>;
+ clocks = <&cpu_ccu CLK_CPU_L>;
enable-method = "psci";
};
@@ -46,6 +50,7 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x300>;
+ clocks = <&cpu_ccu CLK_CPU_L>;
enable-method = "psci";
};
@@ -53,6 +58,7 @@ cpu4: cpu@400 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x400>;
+ clocks = <&cpu_ccu CLK_CPU_B>;
enable-method = "psci";
};
@@ -60,6 +66,7 @@ cpu5: cpu@500 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x500>;
+ clocks = <&cpu_ccu CLK_CPU_B>;
enable-method = "psci";
};
@@ -67,6 +74,7 @@ cpu6: cpu@600 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x600>;
+ clocks = <&cpu_ccu CLK_CPU_B>;
enable-method = "psci";
};
@@ -74,6 +82,7 @@ cpu7: cpu@700 {
compatible = "arm,cortex-a55";
device_type = "cpu";
reg = <0x700>;
+ clocks = <&cpu_ccu CLK_CPU_B>;
enable-method = "psci";
};
};
@@ -1144,5 +1153,18 @@ npu: npu@7122000 {
resets = <&mcu_ccu RST_BUS_MCU_NPU>;
power-domains = <&ppu PD_NPU>;
};
+
+ cpu_ccu: clock-controller@8817000 {
+ compatible = "allwinner,sun55i-a523-cpu-ccu";
+ reg = <0x08817000 0x80>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0_2X>,
+ <&ccu CLK_PLL_PERIPH0_600M>;
+ clock-names = "hosc", "losc",
+ "iosc", "pll-periph0-2x",
+ "pll-periph0-600M";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};