diff mbox series

phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup

Message ID 1368E4E3485E881C+20260706093549.867442-1-raoxu@uniontech.com (mailing list archive)
State New
Headers
Series phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup |

Commit Message

raoxu July 6, 2026, 9:35 a.m. UTC 
From: Xu Rao <raoxu@uniontech.com>

sun4i_usb_phy_init() temporarily enables PHY2's clk2 when a SoC needs
PHY2 SIDDQ setup while initializing another PHY. However, after updating
PHY2's PMU register it disables the clk2 pointer from the PHY currently
being initialized.

This leaves PHY2's clk2 enabled and also drops an extra reference from
the current PHY's clk2, causing the prepare/enable accounting to become
unbalanced.

Disable the same PHY2 clk2 that was enabled for the auxiliary PMU access.

Signed-off-by: Xu Rao <raoxu@uniontech.com>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
2.50.1
diff mbox series

Patch

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index e2fbf8ccf99e..839856c09e30 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -318,7 +318,7 @@  static int sun4i_usb_phy_init(struct phy *_phy)
 			writel(val, phy2->pmu + REG_HCI_PHY_CTL);
 		}

-		clk_disable_unprepare(phy->clk2);
+		clk_disable_unprepare(phy2->clk2);
 	}

 	if (phy->pmu && data->cfg->hci_phy_ctl_clear) {