[v10,5/6] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
Commit Message
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
The interconnects property is used to inherit the proper DMA offset.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
Comments
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `csi0` node introduces the `interconnects` and `interconnect-names` properties, but these are not defined in the corresponding dt-binding schema `allwinner,sun6i-a31-csi.yaml`.
--
commit 6348731e0b0149fecdb9ccb7d05f8577710a1724
Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
This commit adds MIPI CSI-2 support for the V3s SoC by introducing nodes
for CSI0, the MIPI CSI-2 bridge, and the D-PHY. The CSI0 node includes
interconnect properties to inherit the proper DMA offsets.
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> index 02d6c62b3874e..03a1739683b16 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
[ ... ]
> @@ -671,6 +671,79 @@ gic: interrupt-controller@1c81000 {
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + csi0: camera@1cb0000 {
> + compatible = "allwinner,sun8i-v3s-csi";
> + reg = <0x01cb0000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> + interconnects = <&mbus 5>;
> + interconnect-names = "dma-mem";
[Severity: Low]
Will adding these properties cause a dtbs_check validation warning?
The interconnects and interconnect-names properties do not appear to be
defined in the corresponding dt-binding schema at
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml.
Because that schema enforces additionalProperties: false, introducing
undocumented properties here might result in a validation failure. Should
the schema be updated alongside this patch to allow these interconnect
properties?
> + status = "disabled";
> +
[ ... ]
Hi,
Le Sat 13 Jun 26, 15:41, sashiko-bot@kernel.org a écrit :
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] The `csi0` node introduces the `interconnects` and `interconnect-names` properties, but these are not defined in the corresponding dt-binding schema `allwinner,sun6i-a31-csi.yaml`.
> --
>
> commit 6348731e0b0149fecdb9ccb7d05f8577710a1724
> Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
>
> ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
>
> This commit adds MIPI CSI-2 support for the V3s SoC by introducing nodes
> for CSI0, the MIPI CSI-2 bridge, and the D-PHY. The CSI0 node includes
> interconnect properties to inherit the proper DMA offsets.
>
> > diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> > index 02d6c62b3874e..03a1739683b16 100644
> > --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> > +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> [ ... ]
> > @@ -671,6 +671,79 @@ gic: interrupt-controller@1c81000 {
> > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > };
> >
> > + csi0: camera@1cb0000 {
> > + compatible = "allwinner,sun8i-v3s-csi";
> > + reg = <0x01cb0000 0x1000>;
> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CSI>,
> > + <&ccu CLK_CSI_SCLK>,
> > + <&ccu CLK_DRAM_CSI>;
> > + clock-names = "bus", "mod", "ram";
> > + resets = <&ccu RST_BUS_CSI>;
> > + interconnects = <&mbus 5>;
> > + interconnect-names = "dma-mem";
>
> [Severity: Low]
> Will adding these properties cause a dtbs_check validation warning?
>
> The interconnects and interconnect-names properties do not appear to be
> defined in the corresponding dt-binding schema at
> Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml.
Patches to enable said properties in the binding were accepted already.
All the best,
Paul
> Because that schema enforces additionalProperties: false, introducing
> undocumented properties here might result in a validation failure. Should
> the schema be updated alongside this patch to allow these interconnect
> properties?
>
> > + status = "disabled";
> > +
> [ ... ]
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260613152655.212490-1-paulk@sys-base.io?part=5
@@ -671,6 +671,79 @@ gic: interrupt-controller@1c81000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ csi0: camera@1cb0000 {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <&dphy>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint = <&csi0_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun8i-v3s-mipi-dphy",
+ "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CSI>;
+ allwinner,direction = "rx";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;