@@ -119,11 +119,11 @@ examples:
#size-cells = <0>;
panel@0 {
- compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
- reg = <0>;
- power-supply = <®_display>;
- reset-gpios = <&r_pio 0 5 1>; /* PL05 */
- backlight = <&pwm_bl>;
+ compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
+ reg = <0>;
+ power-supply = <®_display>;
+ reset-gpios = <&r_pio 0 5 1>; /* PL05 */
+ backlight = <&pwm_bl>;
};
port {
@@ -84,8 +84,8 @@ examples:
};
mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ reg = <1>;
+ remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
};
};
@@ -107,11 +107,11 @@ examples:
};
port@1 {
- reg = <1>;
+ reg = <1>;
- endpoint {
- remote-endpoint = <&hdmi_in>;
- };
+ endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
};
};
};
@@ -104,7 +104,7 @@ examples:
endpoint {
remote-endpoint = <&stdp2690_in>;
};
- };
+ };
};
};
};
@@ -106,7 +106,7 @@ examples:
video-ports = <0x230145>;
#sound-dai-cells = <1>;
- /* DAI-format / AP_ENA reg value */
+ /* DAI-format / AP_ENA reg value */
audio-ports = <TDA998x_SPDIF 0x04>,
<TDA998x_I2S 0x03>;
@@ -81,7 +81,7 @@ examples:
port@1 {
reg = <1>;
lvds_ep: endpoint {
- remote-endpoint = <&panel_ep>;
+ remote-endpoint = <&panel_ep>;
};
};
};
@@ -161,9 +161,9 @@ examples:
dsi0_out: endpoint {
remote-endpoint = <&d2l_in_test>;
};
- };
- };
- };
+ };
+ };
+ };
- |
/* For dual-link LVDS display panel */
@@ -227,7 +227,7 @@ examples:
dsi0_out_dual: endpoint {
remote-endpoint = <&d2l_in_dual>;
};
- };
- };
- };
+ };
+ };
+ };
...
@@ -74,5 +74,5 @@ examples:
dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
rotation = <90>;
backlight = <&backlight>;
- };
+ };
};
@@ -110,7 +110,7 @@ examples:
port {
parallel_out: endpoint {
- remote-endpoint = <&panel_in>;
+ remote-endpoint = <&panel_in>;
};
};
};
@@ -150,44 +150,44 @@ examples:
/* Using an of-graph endpoint link to connect the panel */
lvds-channel@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
-
- endpoint {
- remote-endpoint = <&ipu_di0_lvds0>;
- };
+ endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
};
+ };
- port@2 {
- reg = <2>;
+ port@2 {
+ reg = <2>;
- endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
/* Using display-timings and fsl,data-mapping/width instead */
lvds-channel@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ display-timings {/* ... */
+ };
+
+ port@1 {
reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- fsl,data-mapping = "spwg";
- fsl,data-width = <24>;
- display-timings {/* ... */
- };
-
- port@1 {
- reg = <1>;
-
- endpoint {
- remote-endpoint = <&ipu_di1_lvds1>;
- };
+ endpoint {
+ remote-endpoint = <&ipu_di1_lvds1>;
};
+ };
};
};
@@ -158,51 +158,51 @@ examples:
#size-cells = <2>;
hdr-engine@1c114000 {
- compatible = "mediatek,mt8195-disp-ethdr";
- reg = <0 0x1c114000 0 0x1000>,
- <0 0x1c115000 0 0x1000>,
- <0 0x1c117000 0 0x1000>,
- <0 0x1c119000 0 0x1000>,
- <0 0x1c11a000 0 0x1000>,
- <0 0x1c11b000 0 0x1000>,
- <0 0x1c11c000 0 0x1000>;
- reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
- "vdo_be", "adl_ds";
- mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
- <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
- clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
- <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
- <&vdosys1 CLK_VDO1_26M_SLOW>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
- <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
- <&topckgen CLK_TOP_ETHDR>;
- clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
- "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
- "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
- "ethdr_top";
- power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
- iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
- <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
- interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
- resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
- <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
- reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
- "gfx_fe1_async", "vdo_be_async";
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11a000 0 0x1000>,
+ <0 0x1c11b000 0 0x1000>,
+ <0 0x1c11c000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
+ "gfx_fe1_async", "vdo_be_async";
};
};
...
@@ -112,24 +112,24 @@ examples:
mediatek,syscon-hdmi = <&mmsys 0x900>;
ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port@0 {
+ reg = <0>;
- hdmi0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
};
- };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- hdmi0_out: endpoint {
- remote-endpoint = <&hdmi_con_in>;
+ hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
};
- };
};
};
@@ -51,7 +51,7 @@ examples:
port {
mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
+ remote-endpoint = <&mipi_out_panel>;
};
};
};
@@ -64,5 +64,5 @@ examples:
vfront-porch = <0>;
vsync-len = <0>;
};
- };
- };
+ };
+ };
@@ -101,35 +101,35 @@ examples:
#size-cells = <0>;
ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- port@0 {
- reg = <0>;
- dsi_in: endpoint {
- remote-endpoint = <<dc_ep1_out>;
- };
- };
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+ };
+ };
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
panel@0 {
- compatible = "orisetech,otm8009a";
- reg = <0>;
- reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
- power-supply = <&v3v3>;
+ compatible = "orisetech,otm8009a";
+ reg = <0>;
+ reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+ power-supply = <&v3v3>;
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
};
};
@@ -119,9 +119,9 @@ examples:
resets = <&rcc LTDC_R>;
port {
- ltdc_out_dsi: endpoint {
- remote-endpoint = <&dsi_in>;
- };
+ ltdc_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
};
};
@@ -114,14 +114,14 @@ examples:
port@0 {
reg = <0>;
lvds_in: endpoint {
- remote-endpoint = <<dc_ep1_out>;
+ remote-endpoint = <<dc_ep1_out>;
};
};
port@1 {
reg = <1>;
lvds_out0: endpoint {
- remote-endpoint = <&lvds_panel_in>;
+ remote-endpoint = <&lvds_panel_in>;
};
};
};