| Message ID | 20260927-submit-h616-emac1-v1-v6-3-e64971f4e414@gmail.com (mailing list archive) |
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From: James Hilliard <james.hilliard1@gmail.com>
Date: Sun, 27 Sep 2026 12:52:21 -0600
Subject: [PATCH net-next v6 3/3] net: stmmac: sun8i: add support for
Allwinner H616 EMAC1
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To: Richard Genoud <richard.genoud@bootlin.com>,
Maxime Chevallier <maxime.chevallier@bootlin.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Chen-Yu Tsai <wens@kernel.org>, Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
LABBE Corentin <clabbe.montjoie@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Jose Abreu <joabreu@synopsys.com>
Cc: Alastair D'Silva <alastair@d-silva.org>,
Maxime Ripard <mripard@kernel.org>,
James Hilliard <james.hilliard1@gmail.com>, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
linux-stm32@st-md-mailman.stormreply.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>
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|
| Series |
net: stmmac: add Allwinner H616 EMAC1 support
|
|
Commit Message
James Hilliard
Sept. 27, 2026, 6:52 p.m. UTC
The H616 secondary EMAC uses a separate system-control clock register and supports only RMII at 10/100 Mbps. It connects internally to the co-packaged AC200 or AC300 EPHY and has no external PHY pins. Add an EMAC1 variant using the dedicated register and enable only RMII. Leave PHY initialization to the PHY driver instead of using the H3 internal-PHY controls. No RX or TX clock delays are configured for this RMII-only variant. Co-developed-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alastair D'Silva <alastair@d-silva.org> Tested-by: Alastair D'Silva <alastair@d-silva.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
Comments
Thank you for your contribution! Sashiko AI review found more severe issue(s) in other patches of this series. This mail is only an FYI, in case you want to address the nit picks below when you respin. Low priority / nit picks for your consideration: - [Low] The new H616 EMAC1 variant (`emac_variant_h616_emac1` in drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c) is meant to be… -- net: stmmac: sun8i: add support for Allwinner H616 EMAC1 This adds an emac_variant for the H616 secondary EMAC. The variant uses a dedicated syscon register at 0x34 and is described as RMII-only at 10/100 Mbps. It is wired internally to the co-packaged AC200/AC300 EPHY. > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > index 5691da796454d..47954537b29e4 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c [ ... ] > @@ -143,6 +150,13 @@ static const struct emac_variant emac_variant_h6 = { > .tx_delay_max = 7, > }; > > +static const struct emac_variant emac_variant_h616_emac1 = { > + .syscon_field = &sun8i_syscon_reg_field_emac1, > + /* The co-packaged AC200/AC300 PHY does not use the H3 PHY controls. */ > + .soc_has_internal_phy = false, > + .support_rmii = true, > +}; [Severity: Low] Does anything actually restrict this variant to RMII? The only place support_mii, support_rmii and support_rgmii appear is in dwmac-sun8i.c: the kernel-doc, the struct emac_variant definition and the variant initializers. Nothing reads them. sun8i_dwmac_set_syscon() picks the register value from plat->phy_interface and does it the same way for every variant: drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c:sun8i_dwmac_set_syscon() { ... switch (plat->phy_interface) { case PHY_INTERFACE_MODE_MII: /* default */ break; case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; break; case PHY_INTERFACE_MODE_RMII: reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; break; ... regmap_field_write(gmac->regmap_field, reg); ... } Suppose a DT node with "allwinner,sun50i-h616-emac1" sets phy-mode to "mii" or "rgmii*". Probe would still succeed, and a value without SYSCON_RMII_EN would be written to the new register at 0x34. This MAC has no external pins. dwmac-sun8i has no get_interfaces callback, so stmmac_phylink_setup() adds the DT-supplied mode to supported_interfaces as is: if (phy_interface_empty(config->supported_interfaces)) __set_bit(priv->plat->phy_interface, config->supported_interfaces); sun8i_dwmac_setup() also always advertises MAC_10 | MAC_100 | MAC_1000 in mac->link.caps. With a non-RMII phy-mode, phylink could then allow gigabit on a 10/100-only MAC. The commit message says: Add an EMAC1 variant using the dedicated register and enable only RMII. There is also no in-tree binding for "allwinner,sun50i-h616-emac1" yet. As far as I can tell, only a correct DT enforces the RMII-only restriction. Older variants such as emac_variant_v3s have the same unchecked flags, but this new variant's RMII-only behaviour depends on them. Would it make sense to reject unsupported phy_interface values in sun8i_dwmac_set_syscon() or at probe? Another option is a get_interfaces callback built from the support_* flags. If neither fits, the commit message could say the restriction comes only from the DT. [ ... ]
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 5691da796454..47954537b29e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -81,6 +81,13 @@ static const struct reg_field sun8i_syscon_reg_field = { .msb = 31, }; +/* EMAC1 clock register @ 0x34 in the "system control" address range */ +static const struct reg_field sun8i_syscon_reg_field_emac1 = { + .reg = 0x34, + .lsb = 0, + .msb = 31, +}; + /* EMAC clock register @ 0x164 in the CCU address range */ static const struct reg_field sun8i_ccu_reg_field = { .reg = 0x164, @@ -143,6 +150,13 @@ static const struct emac_variant emac_variant_h6 = { .tx_delay_max = 7, }; +static const struct emac_variant emac_variant_h616_emac1 = { + .syscon_field = &sun8i_syscon_reg_field_emac1, + /* The co-packaged AC200/AC300 PHY does not use the H3 PHY controls. */ + .soc_has_internal_phy = false, + .support_rmii = true, +}; + #define EMAC_BASIC_CTL0 0x00 #define EMAC_BASIC_CTL1 0x04 #define EMAC_INT_STA 0x08 @@ -1281,6 +1295,8 @@ static const struct of_device_id sun8i_dwmac_match[] = { .data = &emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", .data = &emac_variant_h6 }, + { .compatible = "allwinner,sun50i-h616-emac1", + .data = &emac_variant_h616_emac1 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);