[RFC,net-next,09/10] net: stmmac: clean up test for rx_coe debug printing
Commit Message
The test for printing rx_coe as opposed to rx_coe_type[12] and
rxfifo_over_2048 has checked for an XGMAC core or the Synopssys IP
version (snpsver) >= v4.0.
Since the Synopsys IP version depends on the core type, avoid using it.
The GMAC4 core type uses dwmac4_get_hw_feature(), which populates
rx_coe but not rx_coe_type[12] or rxfifo_over_2048. XGMAC is the same
but via dwxgmac2_get_hw_feature().
dwmac-motorcomm populates rx_coe but not the others, and sets the core
type to GMAC4. The Synopsys IP version is likely >= 4, but in any case
printing rx_coe is clearly more correct.
Lastly, dwmac-sun8i is an oddball - it sets rx_coe, but does not set
core_type, leaving it as the defeault DWMAC_CORE_MAC100 since as far
as I can see, none of the .dtsi files for this platform use any of the
versioned snps,gmac-* compatibles. Moreover, sun8i_dwmac_setup() sets
snpsver to zero (which stmmac_get_version() will have already done) so
this has always used the rx_coe_type[12] path.
Change the test to check for GMAC4 or XGMAC which covers the cases
where rx_coe is set from the core hardware features.
Also add a comment for the GMAC to GMAC4+ rx_coe feature translation in
stmmac_hw_init(), and document rx_coe in struct plat_stmmacenet_data.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 11 +++++++++--
include/linux/stmmac.h | 7 +++++++
2 files changed, 16 insertions(+), 2 deletions(-)
@@ -6624,11 +6624,15 @@ static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
seq_printf(seq, "\tChecksum Offload in TX: %s\n",
(priv->dma_cap.tx_coe) ? "Y" : "N");
- if (priv->snpsver >= DWMAC_CORE_4_00 ||
- priv->plat->core_type == DWMAC_CORE_XGMAC) {
+ if (dwmac_is_xmac(priv->plat->core_type)) {
+ /* gmac4, xgmac, and motorcomm populate this. */
seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
(priv->dma_cap.rx_coe) ? "Y" : "N");
} else {
+ /* only dwmac1000 has these three. sun8i sets rx_coe, but
+ * sets snpsver to zero and leaves core_Type as MAC100, so
+ * uses this path.
+ */
seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
(priv->dma_cap.rx_coe_type1) ? "Y" : "N");
seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
@@ -7441,6 +7445,9 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
/* In case of GMAC4 rx_coe is from HW cap register. */
priv->plat->rx_coe = priv->dma_cap.rx_coe;
+ /* GMAC (dwmac1000) has separate bits for the Rx COE type.
+ * Translate to the GMAC4/XGMAC rx_coe feature code.
+ */
if (priv->dma_cap.rx_coe_type2)
priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
else if (priv->dma_cap.rx_coe_type1)
@@ -256,6 +256,13 @@ struct plat_stmmacenet_data {
bool force_sf_dma_mode;
bool force_thresh_dma_mode;
bool riwt_off;
+ /* rx_coe:
+ * for dwmac100, rx_coe does not appear to be defined.
+ * for dwmac1000, rx_coe takes one of the STMMAC_RX_COE_* constants,
+ * which will be derived from the RXTYP[12]COE hardware feature bits.
+ * for dwmac4 and xgmac, rx_coe is a boolean from the RXCOESEL hardware
+ * feature bit.
+ */
int rx_coe;
int max_speed;
int maxmtu;