[v2,3/3] ARM: dts: sun9i-a80: Add thermal sensor and thermal zones
Commit Message
From: Philipp Rossak <embed3d@gmail.com>
Now that the A80 thermal sensor is supported, add its device node and
the thermal zones to the device tree.
The clocks and the resets are shared between the GPADC and the THS
sensor. Sensor 0 is located beside the big CPU cluster, sensor 1
beside the DRAM controller, sensor 2 beside the GPU and sensor 3
beside the little CPU cluster.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
[soeren: rebased from the 2018 series, fixed the interrupt number
(SPI 115 as in the vendor BSP; verified on hardware - SPI 31 stays
silent), added critical trip points matching the driver's emergency
shutdown threshold]
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Signed-off-by: Sören Hantel <fugininsane@googlemail.com>
---
arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 68 ++++++++++++++++++++++
1 file changed, 68 insertions(+)
Comments
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Thermal zones for CPU clusters are misnamed and cross-mapped relative to the actual CPU cores.
--
--- Patch [3]: [PATCH v2 3/3] ARM: dts: sun9i-a80: Add thermal sensor and thermal zones ---
commit 073b6503b11cee70b348c673193855cbda7082e3
Author: Philipp Rossak <embed3d@gmail.com>
ARM: dts: sun9i-a80: Add thermal sensor and thermal zones
This commit adds the device node for the A80 thermal sensor and defines
the thermal zones in the device tree. It maps the sensors to the big CPU
cluster, DRAM, GPU, and little CPU cluster.
> diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
> index a1ae0929cec9d..8e7f8cd943d2e 100644
> --- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
[ ... ]
> @@ -1250,4 +1260,62 @@ r_rsb: rsb@8003400 {
> #size-cells = <0>;
> };
> };
> +
> + thermal-zones {
> + cpu0_thermal: cpu0-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <5000>;
> + thermal-sensors = <&ths 0>;
[Severity: Medium]
Since cpu0 on the sun9i-a80 is part of the little CPU cluster, does this
map the cpu0 thermal zone to the wrong sensor? The commit message notes
that sensor 0 is beside the big CPU cluster. This could lead to mislabeled
temperatures in userspace and potentially throttle the wrong cluster if
cooling maps are added later.
> +
> + trips {
> + cpu0_crit: cpu0-crit {
> + temperature = <100000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
[ ... ]
> + cpu2_thermal: cpu2-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <5000>;
> + thermal-sensors = <&ths 3>;
[Severity: Medium]
Are these names cross-mapped? This maps cpu2-thermal to sensor 3, which the
commit message states is beside the little CPU cluster. Since cpu2 is also
typically a little core, should the node names better reflect the actual
big/little clusters to avoid confusion?
> +
> + trips {
> + cpu2_crit: cpu2-crit {
> + temperature = <100000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> + };
> };
@@ -941,6 +941,16 @@
#reset-cells = <1>;
};
+ ths: thermal-sensor@6004c00 {
+ compatible = "allwinner,sun9i-a80-ths";
+ reg = <0x06004c00 0x100>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_GPADC>;
+ #thermal-sensor-cells = <1>;
+ };
+
timer@6000c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x06000c00 0xa0>;
@@ -1250,4 +1260,62 @@
#size-cells = <0>;
};
};
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu0_crit: cpu0-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ dram_thermal: dram-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&ths 1>;
+
+ trips {
+ dram_crit: dram-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&ths 2>;
+
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2_thermal: cpu2-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&ths 3>;
+
+ trips {
+ cpu2_crit: cpu2-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};