[6/6] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support
Commit Message
The X96QPro+ TV Box features a Gigabit Ethernet capable port, which is
driven by the secondary EMAC, and supported by a Maxio MAE0621A PHY.
Add the required devicetree nodes to enable that port.
The PHY is not clocked by an external crystal oscillator, but relies on a
SoC-provided clock fanout pin for its 25 MHz reference input clock. The
clock is referenced in the PHY DT node, which not all systems might enable
before scanning the MDIO bus. To help with that problem, the PHY compatible
string is using the PHY ID, which means the MDIO bus scanning can be
skipped.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../dts/allwinner/sun55i-h728-x96qpro+.dts | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
Comments
> +&gmac1 {
> + clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii1_pins>;
> + phy-mode = "rgmii-id";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-supply = <®_cldo3>;
> +
> + tx-internal-delay-ps = <200>;
> + rx-internal-delay-ps = <500>;
500ns is quite big. How did you come to this value? Do you have the
schematic & gerber files? Does the lines look unbalanced?
Andrew
On Tue, Aug 4, 2026 at 10:53 AM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > +&gmac1 {
> > + clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&rgmii1_pins>;
> > + phy-mode = "rgmii-id";
> > + phy-handle = <&ext_rgmii_phy>;
> > + phy-supply = <®_cldo3>;
> > +
> > + tx-internal-delay-ps = <200>;
> > + rx-internal-delay-ps = <500>;
>
> 500ns is quite big. How did you come to this value? Do you have the
> schematic & gerber files? Does the lines look unbalanced?
Unit is ps, not ns.
ChenYu
On Tue, Aug 04, 2026 at 11:11:04AM +0800, Chen-Yu Tsai wrote:
> On Tue, Aug 4, 2026 at 10:53 AM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > +&gmac1 {
> > > + clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&rgmii1_pins>;
> > > + phy-mode = "rgmii-id";
> > > + phy-handle = <&ext_rgmii_phy>;
> > > + phy-supply = <®_cldo3>;
> > > +
> > > + tx-internal-delay-ps = <200>;
> > > + rx-internal-delay-ps = <500>;
> >
> > 500ns is quite big. How did you come to this value? Do you have the
> > schematic & gerber files? Does the lines look unbalanced?
>
> Unit is ps, not ns.
Yes, sorry, wrong units. But still 500ps is very big. You have the PHY
adding 2ns, due to rgmii-id, and you add another 500ps?
Andrew
On Mon, 3 Aug 2026 12:14:52 +0200
Andre Przywara <andre.przywara@arm.com> wrote:
>
> +&mdio1 {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-id7b74.4411";
> + reg = <1>;
> + clocks = <&ccu CLK_EMAC1_25M>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ephy_25m_pin>;
This should be &ephy1_25m_pin, right?
> + reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + reset-deassert-us = <150000>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /*
> PF6 */
@@ -13,6 +13,7 @@ / {
aliases {
serial0 = &uart0;
+ ethernet0 = &gmac1;
};
chosen {
@@ -54,11 +55,38 @@ &ehci1 {
status = "okay";
};
+&gmac1 {
+ clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_cldo3>;
+
+ tx-internal-delay-ps = <200>;
+ rx-internal-delay-ps = <500>;
+
+ status = "okay";
+};
+
&gpu {
mali-supply = <®_dcdc2>;
status = "okay";
};
+&mdio1 {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-id7b74.4411";
+ reg = <1>;
+ clocks = <&ccu CLK_EMAC1_25M>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ephy_25m_pin>;
+ reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <150000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */