| Message ID | 20260428-h616-t113s-hstimer-v3-4-7e02178a93ee@mmpsystems.pl (mailing list archive) |
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| Series | Add hstimer support for H616 and T113-S3 | |
Commit Message
Michal Piekos
April 28, 2026, 4:27 p.m. UTC
Describe high speed timer block on Allwinner H616.
Tested on Orange Pi Zero 3:
- hstimer is registered as clocksource
- switching clocksource at runtime works
- after rating increase hstimer operates as a broadcast clockevent device
Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
---
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
Comments
On Wed, Apr 29, 2026 at 12:29 AM Michal Piekos <michal.piekos@mmpsystems.pl> wrote: > > Describe high speed timer block on Allwinner H616. > > Tested on Orange Pi Zero 3: > - hstimer is registered as clocksource > - switching clocksource at runtime works > - after rating increase hstimer operates as a broadcast clockevent device > > Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index bf054869e78b..1356e5df2562 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -237,6 +237,16 @@ timer0: timer@3009000 { clocks = <&osc24M>; }; + hstimer@3005000 { + compatible = "allwinner,sun50i-h616-hstimer", + "allwinner,sun20i-d1-hstimer"; + reg = <0x03005000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt";